tlb.hh (7734:85a8198aa2ff) | tlb.hh (7749:859e8bc1cdc2) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 194 unchanged lines hidden (view full) --- 203 Fault translateTiming(RequestPtr req, ThreadContext *tc, 204 Translation *translation, Mode mode); 205 206 // Checkpointing 207 void serialize(std::ostream &os); 208 void unserialize(Checkpoint *cp, const std::string §ion); 209 210 void regStats(); | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 194 unchanged lines hidden (view full) --- 203 Fault translateTiming(RequestPtr req, ThreadContext *tc, 204 Translation *translation, Mode mode); 205 206 // Checkpointing 207 void serialize(std::ostream &os); 208 void unserialize(Checkpoint *cp, const std::string §ion); 209 210 void regStats(); |
211 212 // Caching misc register values here. 213 // Writing to misc registers needs to invalidate them. 214 // translateFunctional/translateSe/translateFs checks if they are 215 // invalid and call updateMiscReg if necessary. 216protected: 217 SCTLR sctlr; 218 bool isPriv; 219 uint32_t contextId; 220 PRRR prrr; 221 NMRR nmrr; 222 uint32_t dacr; 223 bool miscRegValid; 224 void updateMiscReg(ThreadContext *tc) 225 { 226 sctlr = tc->readMiscReg(MISCREG_SCTLR); 227 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 228 isPriv = cpsr.mode != MODE_USER; 229 contextId = tc->readMiscReg(MISCREG_CONTEXTIDR); 230 prrr = tc->readMiscReg(MISCREG_PRRR); 231 nmrr = tc->readMiscReg(MISCREG_NMRR); 232 dacr = tc->readMiscReg(MISCREG_DACR); 233 miscRegValid = true; 234 } 235public: 236 inline void invalidateMiscReg() { miscRegValid = false; } |
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211}; 212 213/* namespace ArmISA */ } 214 215#endif // __ARCH_ARM_TLB_HH__ | 237}; 238 239/* namespace ArmISA */ } 240 241#endif // __ARCH_ARM_TLB_HH__ |