tlb.hh (12749:223c83ed9979) tlb.hh (13374:b7f652df5e5b)
1/*
1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
2 * Copyright (c) 2010-2013, 2016, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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147 */
148 static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
149
150 protected:
151 TlbEntry* table; // the Page Table
152 int size; // TLB Size
153 bool isStage2; // Indicates this TLB is part of the second stage MMU
154 bool stage2Req; // Indicates whether a stage 2 lookup is also required
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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147 */
148 static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
149
150 protected:
151 TlbEntry* table; // the Page Table
152 int size; // TLB Size
153 bool isStage2; // Indicates this TLB is part of the second stage MMU
154 bool stage2Req; // Indicates whether a stage 2 lookup is also required
155 // Indicates whether a stage 2 lookup of the table descriptors is required.
156 // Certain address translation instructions will intercept the IPA but the
157 // table descriptors still need to be translated by the stage2.
158 bool stage2DescReq;
155 uint64_t _attr; // Memory attributes for last accessed TLB entry
156 bool directToStage2; // Indicates whether all translation requests should
157 // be routed directly to the stage 2 TLB
158
159 TableWalker *tableWalker;
160 TLB *stage2Tlb;
161 Stage2MMU *stage2Mmu;
162

--- 323 unchanged lines hidden --- 		159 uint64_t _attr; // Memory attributes for last accessed TLB entry
160 bool directToStage2; // Indicates whether all translation requests should
161 // be routed directly to the stage 2 TLB
162
163 TableWalker *tableWalker;
164 TLB *stage2Tlb;
165 Stage2MMU *stage2Mmu;
166

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