tlb.hh (12735:e3da526a0654) | tlb.hh (12749:223c83ed9979) |
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1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 63 unchanged lines hidden (view full) --- 72 /** 73 * Check if a TLB translation should be forced to fail. 74 * 75 * @param req Request requiring a translation. 76 * @param is_priv Access from a privileged mode (i.e., not EL0) 77 * @param mode Access type 78 * @param domain Domain type 79 */ | 1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 63 unchanged lines hidden (view full) --- 72 /** 73 * Check if a TLB translation should be forced to fail. 74 * 75 * @param req Request requiring a translation. 76 * @param is_priv Access from a privileged mode (i.e., not EL0) 77 * @param mode Access type 78 * @param domain Domain type 79 */ |
80 virtual Fault translationCheck(RequestPtr req, bool is_priv, | 80 virtual Fault translationCheck(const RequestPtr &req, bool is_priv, |
81 BaseTLB::Mode mode, 82 TlbEntry::DomainType domain) = 0; 83 84 /** 85 * Check if a page table walker access should be forced to fail. 86 * 87 * @param pa Physical address the walker is accessing 88 * @param size Walker access size --- 133 unchanged lines hidden (view full) --- 222 TableWalker *getTableWalker() { return tableWalker; } 223 224 void setMMU(Stage2MMU *m, MasterID master_id); 225 226 int getsize() const { return size; } 227 228 void insert(Addr vaddr, TlbEntry &pte); 229 | 81 BaseTLB::Mode mode, 82 TlbEntry::DomainType domain) = 0; 83 84 /** 85 * Check if a page table walker access should be forced to fail. 86 * 87 * @param pa Physical address the walker is accessing 88 * @param size Walker access size --- 133 unchanged lines hidden (view full) --- 222 TableWalker *getTableWalker() { return tableWalker; } 223 224 void setMMU(Stage2MMU *m, MasterID master_id); 225 226 int getsize() const { return size; } 227 228 void insert(Addr vaddr, TlbEntry &pte); 229 |
230 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, | 230 Fault getTE(TlbEntry **te, const RequestPtr &req, 231 ThreadContext *tc, Mode mode, |
231 Translation *translation, bool timing, bool functional, 232 bool is_secure, ArmTranslationType tranType); 233 | 232 Translation *translation, bool timing, bool functional, 233 bool is_secure, ArmTranslationType tranType); 234 |
234 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 235 Mode mode, Translation *translation, bool timing, | 235 Fault getResultTe(TlbEntry **te, const RequestPtr &req, 236 ThreadContext *tc, Mode mode, 237 Translation *translation, bool timing, |
236 bool functional, TlbEntry *mergeTe); 237 | 238 bool functional, TlbEntry *mergeTe); 239 |
238 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 239 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, | 240 Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode); 241 Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, |
240 ThreadContext *tc); 241 242 243 /** Reset the entire TLB 244 * @param secure_lookup if the operation affects the secure world 245 */ 246 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 247 bool ignore_el = false); --- 39 unchanged lines hidden (view full) --- 287 * Invalidate all entries in the stage 2 TLB that match the given ipa 288 * and the current VMID 289 * @param ipa the address to invalidate 290 * @param secure_lookup if the operation affects the secure world 291 * @param hyp if the operation affects hyp mode 292 */ 293 void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el); 294 | 242 ThreadContext *tc); 243 244 245 /** Reset the entire TLB 246 * @param secure_lookup if the operation affects the secure world 247 */ 248 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 249 bool ignore_el = false); --- 39 unchanged lines hidden (view full) --- 289 * Invalidate all entries in the stage 2 TLB that match the given ipa 290 * and the current VMID 291 * @param ipa the address to invalidate 292 * @param secure_lookup if the operation affects the secure world 293 * @param hyp if the operation affects hyp mode 294 */ 295 void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el); 296 |
295 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 296 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 297 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); | 297 Fault trickBoxCheck(const RequestPtr &req, Mode mode, 298 TlbEntry::DomainType domain); |
298 | 299 |
300 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, 301 bool is_exec, bool is_write, 302 TlbEntry::DomainType domain, 303 LookupLevel lookup_level); 304 |
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299 void printTlb() const; 300 301 void demapPage(Addr vaddr, uint64_t asn) override 302 { 303 // needed for x86 only 304 panic("demapPage() is not implemented.\n"); 305 } 306 --- 6 unchanged lines hidden (view full) --- 313 * @return if the translation was successful 314 */ 315 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 316 317 /** 318 * Do a functional lookup on the TLB (for checker cpu) that 319 * behaves like a normal lookup without modifying any page table state. 320 */ | 305 void printTlb() const; 306 307 void demapPage(Addr vaddr, uint64_t asn) override 308 { 309 // needed for x86 only 310 panic("demapPage() is not implemented.\n"); 311 } 312 --- 6 unchanged lines hidden (view full) --- 319 * @return if the translation was successful 320 */ 321 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 322 323 /** 324 * Do a functional lookup on the TLB (for checker cpu) that 325 * behaves like a normal lookup without modifying any page table state. 326 */ |
321 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 322 ArmTranslationType tranType); | 327 Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, 328 Mode mode, ArmTranslationType tranType); |
323 Fault | 329 Fault |
324 translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) override | 330 translateFunctional(const RequestPtr &req, 331 ThreadContext *tc, Mode mode) override |
325 { 326 return translateFunctional(req, tc, mode, NormalTran); 327 } 328 329 /** Accessor functions for memory attributes for last accessed TLB entry 330 */ 331 void 332 setAttr(uint64_t attr) 333 { 334 _attr = attr; 335 } 336 337 uint64_t 338 getAttr() const 339 { 340 return _attr; 341 } 342 | 332 { 333 return translateFunctional(req, tc, mode, NormalTran); 334 } 335 336 /** Accessor functions for memory attributes for last accessed TLB entry 337 */ 338 void 339 setAttr(uint64_t attr) 340 { 341 _attr = attr; 342 } 343 344 uint64_t 345 getAttr() const 346 { 347 return _attr; 348 } 349 |
343 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, | 350 Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, |
344 Translation *translation, bool &delay, 345 bool timing, ArmTranslationType tranType, bool functional = false); | 351 Translation *translation, bool &delay, 352 bool timing, ArmTranslationType tranType, bool functional = false); |
346 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, | 353 Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, |
347 Translation *translation, bool &delay, bool timing); | 354 Translation *translation, bool &delay, bool timing); |
348 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, | 355 Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, |
349 ArmTranslationType tranType); 350 Fault | 356 ArmTranslationType tranType); 357 Fault |
351 translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) override | 358 translateAtomic(const RequestPtr &req, 359 ThreadContext *tc, Mode mode) override |
352 { 353 return translateAtomic(req, tc, mode, NormalTran); 354 } 355 void translateTiming( | 360 { 361 return translateAtomic(req, tc, mode, NormalTran); 362 } 363 void translateTiming( |
356 RequestPtr req, ThreadContext *tc, | 364 const RequestPtr &req, ThreadContext *tc, |
357 Translation *translation, Mode mode, 358 ArmTranslationType tranType); 359 void | 365 Translation *translation, Mode mode, 366 ArmTranslationType tranType); 367 void |
360 translateTiming(RequestPtr req, ThreadContext *tc, | 368 translateTiming(const RequestPtr &req, ThreadContext *tc, |
361 Translation *translation, Mode mode) override 362 { 363 translateTiming(req, tc, translation, mode, NormalTran); 364 } | 369 Translation *translation, Mode mode) override 370 { 371 translateTiming(req, tc, translation, mode, NormalTran); 372 } |
365 Fault translateComplete(RequestPtr req, ThreadContext *tc, | 373 Fault translateComplete(const RequestPtr &req, ThreadContext *tc, |
366 Translation *translation, Mode mode, ArmTranslationType tranType, 367 bool callFromS2); 368 Fault finalizePhysical( | 374 Translation *translation, Mode mode, ArmTranslationType tranType, 375 bool callFromS2); 376 Fault finalizePhysical( |
369 RequestPtr req, ThreadContext *tc, Mode mode) const override; | 377 const RequestPtr &req, 378 ThreadContext *tc, Mode mode) const override; |
370 371 void drainResume() override; 372 373 // Checkpointing 374 void serialize(CheckpointOut &cp) const override; 375 void unserialize(CheckpointIn &cp) override; 376 377 void regStats() override; --- 63 unchanged lines hidden (view full) --- 441 * @param ignore_asn if the flush should ignore the asn 442 */ 443 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 444 bool hyp, bool ignore_asn, uint8_t target_el); 445 446 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 447 448 public: /* Testing */ | 379 380 void drainResume() override; 381 382 // Checkpointing 383 void serialize(CheckpointOut &cp) const override; 384 void unserialize(CheckpointIn &cp) override; 385 386 void regStats() override; --- 63 unchanged lines hidden (view full) --- 450 * @param ignore_asn if the flush should ignore the asn 451 */ 452 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 453 bool hyp, bool ignore_asn, uint8_t target_el); 454 455 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 456 457 public: /* Testing */ |
449 Fault testTranslation(RequestPtr req, Mode mode, | 458 Fault testTranslation(const RequestPtr &req, Mode mode, |
450 TlbEntry::DomainType domain); 451 Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 452 TlbEntry::DomainType domain, 453 LookupLevel lookup_level); 454}; 455 456template<typename T> 457TLB * --- 19 unchanged lines hidden --- | 459 TlbEntry::DomainType domain); 460 Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 461 TlbEntry::DomainType domain, 462 LookupLevel lookup_level); 463}; 464 465template<typename T> 466TLB * --- 19 unchanged lines hidden --- |