tlb.hh (11395:032bc62120eb) tlb.hh (11577:a26a328c20eb)
1/*
1/*
2 * Copyright (c) 2010-2013 ARM Limited
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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122 };
123
124 enum ArmTranslationType {
125 NormalTran = 0,
126 S1CTran = 0x1,
127 HypMode = 0x2,
128 // Secure code operating as if it wasn't (required by some Address
129 // Translate operations)
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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122 };
123
124 enum ArmTranslationType {
125 NormalTran = 0,
126 S1CTran = 0x1,
127 HypMode = 0x2,
128 // Secure code operating as if it wasn't (required by some Address
129 // Translate operations)
130 S1S2NsTran = 0x4
130 S1S2NsTran = 0x4,
131 // Address translation instructions (eg AT S1E0R_Xt) need to be handled
132 // in special ways during translation because they could need to act
133 // like a different EL than the current EL. The following flags are
134 // for these instructions
135 S1E0Tran = 0x8,
136 S1E1Tran = 0x10,
137 S1E2Tran = 0x20,
138 S1E3Tran = 0x40,
139 S12E0Tran = 0x80,
140 S12E1Tran = 0x100
131 };
132 protected:
133 TlbEntry* table; // the Page Table
134 int size; // TLB Size
135 bool isStage2; // Indicates this TLB is part of the second stage MMU
136 bool stage2Req; // Indicates whether a stage 2 lookup is also required
137 uint64_t _attr; // Memory attributes for last accessed TLB entry
138 bool directToStage2; // Indicates whether all translation requests should

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141 };
142 protected:
143 TlbEntry* table; // the Page Table
144 int size; // TLB Size
145 bool isStage2; // Indicates this TLB is part of the second stage MMU
146 bool stage2Req; // Indicates whether a stage 2 lookup is also required
147 uint64_t _attr; // Memory attributes for last accessed TLB entry
148 bool directToStage2; // Indicates whether all translation requests should

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