tlb.hh (11168:f98eb2da15a4) tlb.hh (11169:44b5c183c3cd)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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150 * @return pointer to TLB entry if it exists
151 */
152 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
153 bool secure, bool functional,
154 bool ignore_asn, uint8_t target_el);
155
156 virtual ~TLB();
157
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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150 * @return pointer to TLB entry if it exists
151 */
152 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
153 bool secure, bool functional,
154 bool ignore_asn, uint8_t target_el);
155
156 virtual ~TLB();
157
158 void takeOverFrom(BaseTLB *otlb);
158 void takeOverFrom(BaseTLB *otlb) override;
159
160 /// setup all the back pointers
159
160 /// setup all the back pointers
161 virtual void init();
161 void init() override;
162
163 TableWalker *getTableWalker() { return tableWalker; }
164
165 void setMMU(Stage2MMU *m, MasterID master_id);
166
167 int getsize() const { return size; }
168
169 void insert(Addr vaddr, TlbEntry &pte);

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192 * @param hyp if the opperation affects hyp mode
193 */
194 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
195
196
197 /** Reset the entire TLB. Used for CPU switching to prevent stale
198 * translations after multiple switches
199 */
162
163 TableWalker *getTableWalker() { return tableWalker; }
164
165 void setMMU(Stage2MMU *m, MasterID master_id);
166
167 int getsize() const { return size; }
168
169 void insert(Addr vaddr, TlbEntry &pte);

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192 * @param hyp if the opperation affects hyp mode
193 */
194 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
195
196
197 /** Reset the entire TLB. Used for CPU switching to prevent stale
198 * translations after multiple switches
199 */
200 void flushAll()
200 void flushAll() override
201 {
202 flushAllSecurity(false, 0, true);
203 flushAllSecurity(true, 0, true);
204 }
205
206 /** Remove any entries that match both a va and asn
207 * @param mva virtual address to flush
208 * @param asn contextid/asn to flush on match

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225 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
226
227 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
228 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
229 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
230
231 void printTlb() const;
232
201 {
202 flushAllSecurity(false, 0, true);
203 flushAllSecurity(true, 0, true);
204 }
205
206 /** Remove any entries that match both a va and asn
207 * @param mva virtual address to flush
208 * @param asn contextid/asn to flush on match

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225 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
226
227 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
228 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
229 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
230
231 void printTlb() const;
232
233 void demapPage(Addr vaddr, uint64_t asn)
233 void demapPage(Addr vaddr, uint64_t asn) override
234 {
235 // needed for x86 only
236 panic("demapPage() is not implemented.\n");
237 }
238
234 {
235 // needed for x86 only
236 panic("demapPage() is not implemented.\n");
237 }
238
239 static bool validVirtualAddress(Addr vaddr);
240
241 /**
242 * Do a functional lookup on the TLB (for debugging)
243 * and don't modify any internal state
244 * @param tc thread context to get the context id from
245 * @param vaddr virtual address to translate
246 * @param pa returned physical address
247 * @return if the translation was successful
248 */

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285 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
286
287 void drainResume() override;
288
289 // Checkpointing
290 void serialize(CheckpointOut &cp) const override;
291 void unserialize(CheckpointIn &cp) override;
292
239 /**
240 * Do a functional lookup on the TLB (for debugging)
241 * and don't modify any internal state
242 * @param tc thread context to get the context id from
243 * @param vaddr virtual address to translate
244 * @param pa returned physical address
245 * @return if the translation was successful
246 */

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283 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
284
285 void drainResume() override;
286
287 // Checkpointing
288 void serialize(CheckpointOut &cp) const override;
289 void unserialize(CheckpointIn &cp) override;
290
293 void regStats();
291 void regStats() override;
294
295 void regProbePoints() override;
296
297 /**
298 * Get the table walker master port. This is used for migrating
299 * port connections during a CPU takeOverFrom() call. For
300 * architectures that do not have a table walker, NULL is
301 * returned, hence the use of a pointer rather than a
302 * reference. For ARM this method will always return a valid port
303 * pointer.
304 *
305 * @return A pointer to the walker master port
306 */
292
293 void regProbePoints() override;
294
295 /**
296 * Get the table walker master port. This is used for migrating
297 * port connections during a CPU takeOverFrom() call. For
298 * architectures that do not have a table walker, NULL is
299 * returned, hence the use of a pointer rather than a
300 * reference. For ARM this method will always return a valid port
301 * pointer.
302 *
303 * @return A pointer to the walker master port
304 */
307 virtual BaseMasterPort* getMasterPort();
305 BaseMasterPort* getMasterPort() override;
308
309 // Caching misc register values here.
310 // Writing to misc registers needs to invalidate them.
311 // translateFunctional/translateSe/translateFs checks if they are
312 // invalid and call updateMiscReg if necessary.
313protected:
314 CPSR cpsr;
315 bool aarch64;

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307 // Caching misc register values here.
308 // Writing to misc registers needs to invalidate them.
309 // translateFunctional/translateSe/translateFs checks if they are
310 // invalid and call updateMiscReg if necessary.
311protected:
312 CPSR cpsr;
313 bool aarch64;

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