1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 45 unchanged lines hidden (view full) --- 54#include "params/ArmTLB.hh" 55#include "sim/faults.hh" 56#include "sim/tlb.hh" 57 58class ThreadContext; 59 60namespace ArmISA { 61 |
62class TableWalker; 63 |
64class TLB : public BaseTLB 65{ 66 public: 67 enum ArmFlags { 68 AlignmentMask = 0x7, 69 70 AlignByte = 0x0, 71 AlignHalfWord = 0x1, 72 AlignWord = 0x3, 73 AlignDoubleWord = 0x7, 74 75 AllowUnaligned = 0x8, |
76 // Priv code operating as if it wasn't 77 UserMode = 0x10, |
78 // Because zero otherwise looks like a valid setting and may be used 79 // accidentally, this bit must be non-zero to show it was used on 80 // purpose. |
81 MustBeOne = 0x20 |
82 }; 83 protected: 84 typedef std::multimap<Addr, int> PageTable; 85 PageTable lookupTable; // Quick lookup into page table 86 |
87 TlbEntry *table; // the Page Table |
88 int size; // TLB Size 89 int nlu; // not last used entry (for replacement) |
90 TableWalker *tableWalker; |
91 92 void nextnlu() { if (++nlu >= size) nlu = 0; } |
93 TlbEntry *lookup(Addr vpn, uint8_t asn); |
94 95 // Access Stats 96 mutable Stats::Scalar read_hits; 97 mutable Stats::Scalar read_misses; 98 mutable Stats::Scalar read_acv; 99 mutable Stats::Scalar read_accesses; 100 mutable Stats::Scalar write_hits; 101 mutable Stats::Scalar write_misses; 102 mutable Stats::Scalar write_acv; 103 mutable Stats::Scalar write_accesses; 104 Stats::Formula hits; 105 Stats::Formula misses; 106 Stats::Formula invalids; 107 Stats::Formula accesses; 108 |
109 |
110 public: 111 typedef ArmTLBParams Params; 112 TLB(const Params *p); 113 114 virtual ~TLB(); 115 int getsize() const { return size; } 116 |
117 void insert(Addr vaddr, TlbEntry &pte); 118 119 /** Reset the entire TLB */ |
120 void flushAll(); |
121 122 /** Remove any entries that match both a va and asn 123 * @param mva virtual address to flush 124 * @param asn contextid/asn to flush on match 125 */ 126 void flushMvaAsid(Addr mva, uint64_t asn); 127 128 /** Remove any entries that match the asn 129 * @param asn contextid/asn to flush on match 130 */ 131 void flushAsid(uint64_t asn); 132 133 /** Remove all entries that match the va regardless of asn 134 * @param mva address to flush from cache 135 */ 136 void flushMva(Addr mva); 137 138 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp); 139 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, uint8_t 140 domain, bool sNp); 141 142 void printTlb(); 143 |
144 void demapPage(Addr vaddr, uint64_t asn) 145 { |
146 flushMvaAsid(vaddr, asn); |
147 } 148 149 static bool validVirtualAddress(Addr vaddr); 150 |
151#if FULL_SYSTEM 152 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 153 Translation *translation, bool &delay, bool timing); 154#else 155 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 156 Translation *translation, bool &delay, bool timing); 157#endif |
158 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); |
159 Fault translateTiming(RequestPtr req, ThreadContext *tc, |
160 Translation *translation, Mode mode); 161 162 // Checkpointing 163 void serialize(std::ostream &os); 164 void unserialize(Checkpoint *cp, const std::string §ion); 165 166 void regStats(); 167}; 168 169/* namespace ArmISA */ } 170 171#endif // __ARCH_ARM_TLB_HH__ |