2c2
< * Copyright (c) 2010-2012 ARM Limited
---
> * Copyright (c) 2010-2013 ARM Limited
46d45
< #include <map>
52a52
> #include "dev/dma_device.hh"
62a63,64
> class Stage2LookUp;
> class Stage2MMU;
68c70
< AlignmentMask = 0x1f,
---
> AlignmentMask = 0x7,
72,75c74,77
< AlignWord = 0x3,
< AlignDoubleWord = 0x7,
< AlignQuadWord = 0xf,
< AlignOctWord = 0x1f,
---
> AlignWord = 0x2,
> AlignDoubleWord = 0x3,
> AlignQuadWord = 0x4,
> AlignOctWord = 0x5,
77c79
< AllowUnaligned = 0x20,
---
> AllowUnaligned = 0x8,
79c81
< UserMode = 0x40,
---
> UserMode = 0x10,
83c85
< MustBeOne = 0x80
---
> MustBeOne = 0x40
84a87,95
>
> enum ArmTranslationType {
> NormalTran = 0,
> S1CTran = 0x1,
> HypMode = 0x2,
> // Secure code operating as if it wasn't (required by some Address
> // Translate operations)
> S1S2NsTran = 0x4
> };
85a97,103
> TlbEntry* table; // the Page Table
> int size; // TLB Size
> bool isStage2; // Indicates this TLB is part of the second stage MMU
> bool stage2Req; // Indicates whether a stage 2 lookup is also required
> uint64_t _attr; // Memory attributes for last accessed TLB entry
> bool directToStage2; // Indicates whether all translation requests should
> // be routed directly to the stage 2 TLB
87,91d104
< TlbEntry *table; // the Page Table
< int size; // TLB Size
<
< uint32_t _attr; // Memory attributes for last accessed TLB entry
<
92a106,107
> TLB *stage2Tlb;
> Stage2MMU *stage2Mmu;
124,125c139,140
< typedef ArmTLBParams Params;
< TLB(const Params *p);
---
> TLB(const ArmTLBParams *p);
> TLB(const Params *p, int _size, TableWalker *_walker);
129a145,147
> * @param vmid The virtual machine ID used for stage 2 translation
> * @param secure if the lookup is secure
> * @param hyp if the lookup is done from hyp mode
131c149,150
< * @return pointer to TLB entrry if it exists
---
> * @param ignore_asn if on lookup asn should be ignored
> * @return pointer to TLB entry if it exists
133c152,154
< TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
---
> TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
> bool secure, bool functional,
> bool ignore_asn, uint8_t target_el);
135a157,162
>
> /// setup all the back pointers
> virtual void init();
>
> void setMMU(Stage2MMU *m);
>
140,141c167,169
< /** Reset the entire TLB */
< void flushAll();
---
> Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
> Translation *translation, bool timing, bool functional,
> bool is_secure, ArmTranslationType tranType);
142a171,201
> Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
> Mode mode, Translation *translation, bool timing,
> bool functional, TlbEntry *mergeTe);
>
> Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
> Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
> ThreadContext *tc);
>
>
> /** Reset the entire TLB
> * @param secure_lookup if the operation affects the secure world
> */
> void flushAllSecurity(bool secure_lookup, uint8_t target_el,
> bool ignore_el = false);
>
> /** Remove all entries in the non secure world, depending on whether they
> * were allocated in hyp mode or not
> * @param hyp if the opperation affects hyp mode
> */
> void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
>
>
> /** Reset the entire TLB. Used for CPU switching to prevent stale
> * translations after multiple switches
> */
> void flushAll()
> {
> flushAllSecurity(false, 0, true);
> flushAllSecurity(true, 0, true);
> }
>
145a205
> * @param secure_lookup if the operation affects the secure world
147c207,208
< void flushMvaAsid(Addr mva, uint64_t asn);
---
> void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
> uint8_t target_el);
150a212
> * @param secure_lookup if the operation affects the secure world
152c214
< void flushAsid(uint64_t asn);
---
> void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
155a218,219
> * @param secure_lookup if the operation affects the secure world
> * @param hyp if the operation affects hyp mode
157c221
< void flushMva(Addr mva);
---
> void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
159,161c223,225
< Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
< Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
< bool is_write, uint8_t domain, bool sNp);
---
> Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
> Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
> bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
163c227
< void printTlb();
---
> void printTlb() const;
168c232,233
< flushMvaAsid(vaddr, asn);
---
> // needed for x86 only
> panic("demapPage() is not implemented.\n");
187c252,253
< Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
---
> Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
> ArmTranslationType tranType = NormalTran);
192c258
< setAttr(uint32_t attr)
---
> setAttr(uint64_t attr)
196c262,263
< uint32_t
---
>
> uint64_t
204c271
< bool timing, bool functional = false);
---
> bool timing, ArmTranslationType tranType, bool functional = false);
207c274,275
< Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
---
> Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
> ArmTranslationType tranType = NormalTran);
209c277,281
< Translation *translation, Mode mode);
---
> Translation *translation, Mode mode,
> ArmTranslationType tranType = NormalTran);
> Fault translateComplete(RequestPtr req, ThreadContext *tc,
> Translation *translation, Mode mode, ArmTranslationType tranType,
> bool callFromS2);
231a304,312
> /**
> * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
> * access the table walker port of this TLB so that it can
> * orchestrate staged translations.
> *
> * @return The table walker DMA port
> */
> DmaPort& getWalkerPort();
>
236a318,319
> bool aarch64;
> ExceptionLevel aarch64EL;
237a321
> SCR scr;
239c323,327
< CONTEXTIDR contextId;
---
> bool isSecure;
> bool isHyp;
> TTBCR ttbcr;
> uint16_t asid;
> uint8_t vmid;
241a330
> HCR hcr;
244,254c333,342
< void updateMiscReg(ThreadContext *tc)
< {
< sctlr = tc->readMiscReg(MISCREG_SCTLR);
< CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
< isPriv = cpsr.mode != MODE_USER;
< contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
< prrr = tc->readMiscReg(MISCREG_PRRR);
< nmrr = tc->readMiscReg(MISCREG_NMRR);
< dacr = tc->readMiscReg(MISCREG_DACR);
< miscRegValid = true;
< }
---
> ArmTranslationType curTranType;
>
> // Cached copies of system-level properties
> bool haveLPAE;
> bool haveVirtualization;
> bool haveLargeAsid64;
>
> void updateMiscReg(ThreadContext *tc,
> ArmTranslationType tranType = NormalTran);
>
261a350,362
>
> private:
> /** Remove any entries that match both a va and asn
> * @param mva virtual address to flush
> * @param asn contextid/asn to flush on match
> * @param secure_lookup if the operation affects the secure world
> * @param hyp if the operation affects hyp mode
> * @param ignore_asn if the flush should ignore the asn
> */
> void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
> bool hyp, bool ignore_asn, uint8_t target_el);
>
> bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
< * Copyright (c) 2010-2012 ARM Limited
---
> * Copyright (c) 2010-2013 ARM Limited
46d45
< #include <map>
52a52
> #include "dev/dma_device.hh"
62a63,64
> class Stage2LookUp;
> class Stage2MMU;
68c70
< AlignmentMask = 0x1f,
---
> AlignmentMask = 0x7,
72,75c74,77
< AlignWord = 0x3,
< AlignDoubleWord = 0x7,
< AlignQuadWord = 0xf,
< AlignOctWord = 0x1f,
---
> AlignWord = 0x2,
> AlignDoubleWord = 0x3,
> AlignQuadWord = 0x4,
> AlignOctWord = 0x5,
77c79
< AllowUnaligned = 0x20,
---
> AllowUnaligned = 0x8,
79c81
< UserMode = 0x40,
---
> UserMode = 0x10,
83c85
< MustBeOne = 0x80
---
> MustBeOne = 0x40
84a87,95
>
> enum ArmTranslationType {
> NormalTran = 0,
> S1CTran = 0x1,
> HypMode = 0x2,
> // Secure code operating as if it wasn't (required by some Address
> // Translate operations)
> S1S2NsTran = 0x4
> };
85a97,103
> TlbEntry* table; // the Page Table
> int size; // TLB Size
> bool isStage2; // Indicates this TLB is part of the second stage MMU
> bool stage2Req; // Indicates whether a stage 2 lookup is also required
> uint64_t _attr; // Memory attributes for last accessed TLB entry
> bool directToStage2; // Indicates whether all translation requests should
> // be routed directly to the stage 2 TLB
87,91d104
< TlbEntry *table; // the Page Table
< int size; // TLB Size
<
< uint32_t _attr; // Memory attributes for last accessed TLB entry
<
92a106,107
> TLB *stage2Tlb;
> Stage2MMU *stage2Mmu;
124,125c139,140
< typedef ArmTLBParams Params;
< TLB(const Params *p);
---
> TLB(const ArmTLBParams *p);
> TLB(const Params *p, int _size, TableWalker *_walker);
129a145,147
> * @param vmid The virtual machine ID used for stage 2 translation
> * @param secure if the lookup is secure
> * @param hyp if the lookup is done from hyp mode
131c149,150
< * @return pointer to TLB entrry if it exists
---
> * @param ignore_asn if on lookup asn should be ignored
> * @return pointer to TLB entry if it exists
133c152,154
< TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
---
> TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
> bool secure, bool functional,
> bool ignore_asn, uint8_t target_el);
135a157,162
>
> /// setup all the back pointers
> virtual void init();
>
> void setMMU(Stage2MMU *m);
>
140,141c167,169
< /** Reset the entire TLB */
< void flushAll();
---
> Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
> Translation *translation, bool timing, bool functional,
> bool is_secure, ArmTranslationType tranType);
142a171,201
> Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
> Mode mode, Translation *translation, bool timing,
> bool functional, TlbEntry *mergeTe);
>
> Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
> Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
> ThreadContext *tc);
>
>
> /** Reset the entire TLB
> * @param secure_lookup if the operation affects the secure world
> */
> void flushAllSecurity(bool secure_lookup, uint8_t target_el,
> bool ignore_el = false);
>
> /** Remove all entries in the non secure world, depending on whether they
> * were allocated in hyp mode or not
> * @param hyp if the opperation affects hyp mode
> */
> void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
>
>
> /** Reset the entire TLB. Used for CPU switching to prevent stale
> * translations after multiple switches
> */
> void flushAll()
> {
> flushAllSecurity(false, 0, true);
> flushAllSecurity(true, 0, true);
> }
>
145a205
> * @param secure_lookup if the operation affects the secure world
147c207,208
< void flushMvaAsid(Addr mva, uint64_t asn);
---
> void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
> uint8_t target_el);
150a212
> * @param secure_lookup if the operation affects the secure world
152c214
< void flushAsid(uint64_t asn);
---
> void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
155a218,219
> * @param secure_lookup if the operation affects the secure world
> * @param hyp if the operation affects hyp mode
157c221
< void flushMva(Addr mva);
---
> void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
159,161c223,225
< Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
< Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
< bool is_write, uint8_t domain, bool sNp);
---
> Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
> Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
> bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
163c227
< void printTlb();
---
> void printTlb() const;
168c232,233
< flushMvaAsid(vaddr, asn);
---
> // needed for x86 only
> panic("demapPage() is not implemented.\n");
187c252,253
< Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
---
> Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
> ArmTranslationType tranType = NormalTran);
192c258
< setAttr(uint32_t attr)
---
> setAttr(uint64_t attr)
196c262,263
< uint32_t
---
>
> uint64_t
204c271
< bool timing, bool functional = false);
---
> bool timing, ArmTranslationType tranType, bool functional = false);
207c274,275
< Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
---
> Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
> ArmTranslationType tranType = NormalTran);
209c277,281
< Translation *translation, Mode mode);
---
> Translation *translation, Mode mode,
> ArmTranslationType tranType = NormalTran);
> Fault translateComplete(RequestPtr req, ThreadContext *tc,
> Translation *translation, Mode mode, ArmTranslationType tranType,
> bool callFromS2);
231a304,312
> /**
> * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
> * access the table walker port of this TLB so that it can
> * orchestrate staged translations.
> *
> * @return The table walker DMA port
> */
> DmaPort& getWalkerPort();
>
236a318,319
> bool aarch64;
> ExceptionLevel aarch64EL;
237a321
> SCR scr;
239c323,327
< CONTEXTIDR contextId;
---
> bool isSecure;
> bool isHyp;
> TTBCR ttbcr;
> uint16_t asid;
> uint8_t vmid;
241a330
> HCR hcr;
244,254c333,342
< void updateMiscReg(ThreadContext *tc)
< {
< sctlr = tc->readMiscReg(MISCREG_SCTLR);
< CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
< isPriv = cpsr.mode != MODE_USER;
< contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
< prrr = tc->readMiscReg(MISCREG_PRRR);
< nmrr = tc->readMiscReg(MISCREG_NMRR);
< dacr = tc->readMiscReg(MISCREG_DACR);
< miscRegValid = true;
< }
---
> ArmTranslationType curTranType;
>
> // Cached copies of system-level properties
> bool haveLPAE;
> bool haveVirtualization;
> bool haveLargeAsid64;
>
> void updateMiscReg(ThreadContext *tc,
> ArmTranslationType tranType = NormalTran);
>
261a350,362
>
> private:
> /** Remove any entries that match both a va and asn
> * @param mva virtual address to flush
> * @param asn contextid/asn to flush on match
> * @param secure_lookup if the operation affects the secure world
> * @param hyp if the operation affects hyp mode
> * @param ignore_asn if the flush should ignore the asn
> */
> void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
> bool hyp, bool ignore_asn, uint8_t target_el);
>
> bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);