1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46#include <map>
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/arm/pagetable.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/fault.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
63
64class TLB : public BaseTLB
65{
66 public:
67 enum ArmFlags {
68 AlignmentMask = 0x1f,
69
70 AlignByte = 0x0,
71 AlignHalfWord = 0x1,
72 AlignWord = 0x3,
73 AlignDoubleWord = 0x7,
74 AlignQuadWord = 0xf,
75 AlignOctWord = 0x1f,
76
77 AllowUnaligned = 0x20,
78 // Priv code operating as if it wasn't
79 UserMode = 0x40,
80 // Because zero otherwise looks like a valid setting and may be used
81 // accidentally, this bit must be non-zero to show it was used on
82 // purpose.
83 MustBeOne = 0x80
84 };
85 protected:
86 typedef std::multimap<Addr, int> PageTable;
87 PageTable lookupTable; // Quick lookup into page table
88
89 TlbEntry *table; // the Page Table
90 int size; // TLB Size
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46#include <map>
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/arm/pagetable.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/fault.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
63
64class TLB : public BaseTLB
65{
66 public:
67 enum ArmFlags {
68 AlignmentMask = 0x1f,
69
70 AlignByte = 0x0,
71 AlignHalfWord = 0x1,
72 AlignWord = 0x3,
73 AlignDoubleWord = 0x7,
74 AlignQuadWord = 0xf,
75 AlignOctWord = 0x1f,
76
77 AllowUnaligned = 0x20,
78 // Priv code operating as if it wasn't
79 UserMode = 0x40,
80 // Because zero otherwise looks like a valid setting and may be used
81 // accidentally, this bit must be non-zero to show it was used on
82 // purpose.
83 MustBeOne = 0x80
84 };
85 protected:
86 typedef std::multimap<Addr, int> PageTable;
87 PageTable lookupTable; // Quick lookup into page table
88
89 TlbEntry *table; // the Page Table
90 int size; // TLB Size
|
91 int nlu; // not last used entry (for replacement)
| |
92
93 uint32_t _attr; // Memory attributes for last accessed TLB entry
94
95#if FULL_SYSTEM
96 TableWalker *tableWalker;
97#endif
98
| 91
92 uint32_t _attr; // Memory attributes for last accessed TLB entry
93
94#if FULL_SYSTEM
95 TableWalker *tableWalker;
96#endif
97
|
99 void nextnlu() { if (++nlu >= size) nlu = 0; }
| |
100 /** Lookup an entry in the TLB
101 * @param vpn virtual address
102 * @param asn context id/address space id to use
103 * @param functional if the lookup should modify state
104 * @return pointer to TLB entrry if it exists
105 */
106 TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
107
108 // Access Stats
109 mutable Stats::Scalar read_hits;
110 mutable Stats::Scalar read_misses;
111 mutable Stats::Scalar read_acv;
112 mutable Stats::Scalar read_accesses;
113 mutable Stats::Scalar write_hits;
114 mutable Stats::Scalar write_misses;
115 mutable Stats::Scalar write_acv;
116 mutable Stats::Scalar write_accesses;
117 Stats::Formula hits;
118 Stats::Formula misses;
119 Stats::Formula accesses;
120
| 98 /** Lookup an entry in the TLB
99 * @param vpn virtual address
100 * @param asn context id/address space id to use
101 * @param functional if the lookup should modify state
102 * @return pointer to TLB entrry if it exists
103 */
104 TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
105
106 // Access Stats
107 mutable Stats::Scalar read_hits;
108 mutable Stats::Scalar read_misses;
109 mutable Stats::Scalar read_acv;
110 mutable Stats::Scalar read_accesses;
111 mutable Stats::Scalar write_hits;
112 mutable Stats::Scalar write_misses;
113 mutable Stats::Scalar write_acv;
114 mutable Stats::Scalar write_accesses;
115 Stats::Formula hits;
116 Stats::Formula misses;
117 Stats::Formula accesses;
118
|
| 119 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
|
121
122 public:
123 typedef ArmTLBParams Params;
124 TLB(const Params *p);
125
126 virtual ~TLB();
127 int getsize() const { return size; }
128
129 void insert(Addr vaddr, TlbEntry &pte);
130
131 /** Reset the entire TLB */
132 void flushAll();
133
134 /** Remove any entries that match both a va and asn
135 * @param mva virtual address to flush
136 * @param asn contextid/asn to flush on match
137 */
138 void flushMvaAsid(Addr mva, uint64_t asn);
139
140 /** Remove any entries that match the asn
141 * @param asn contextid/asn to flush on match
142 */
143 void flushAsid(uint64_t asn);
144
145 /** Remove all entries that match the va regardless of asn
146 * @param mva address to flush from cache
147 */
148 void flushMva(Addr mva);
149
150 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
151 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
152 bool is_write, uint8_t domain, bool sNp);
153
154 void printTlb();
155
156 void demapPage(Addr vaddr, uint64_t asn)
157 {
158 flushMvaAsid(vaddr, asn);
159 }
160
161 static bool validVirtualAddress(Addr vaddr);
162
163 /**
164 * Do a functional lookup on the TLB (for debugging)
165 * and don't modify any internal state
166 * @param tc thread context to get the context id from
167 * @param vaddr virtual address to translate
168 * @param pa returned physical address
169 * @return if the translation was successful
170 */
171 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
172
173 /** Accessor functions for memory attributes for last accessed TLB entry
174 */
175 void
176 setAttr(uint32_t attr)
177 {
178 _attr = attr;
179 }
180 uint32_t
181 getAttr() const
182 {
183 return _attr;
184 }
185
186#if FULL_SYSTEM
187 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
188 Translation *translation, bool &delay, bool timing);
189#else
190 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
191 Translation *translation, bool &delay, bool timing);
192#endif
193 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
194 Fault translateTiming(RequestPtr req, ThreadContext *tc,
195 Translation *translation, Mode mode);
196
197 // Checkpointing
198 void serialize(std::ostream &os);
199 void unserialize(Checkpoint *cp, const std::string §ion);
200
201 void regStats();
202};
203
204/* namespace ArmISA */ }
205
206#endif // __ARCH_ARM_TLB_HH__
| 120
121 public:
122 typedef ArmTLBParams Params;
123 TLB(const Params *p);
124
125 virtual ~TLB();
126 int getsize() const { return size; }
127
128 void insert(Addr vaddr, TlbEntry &pte);
129
130 /** Reset the entire TLB */
131 void flushAll();
132
133 /** Remove any entries that match both a va and asn
134 * @param mva virtual address to flush
135 * @param asn contextid/asn to flush on match
136 */
137 void flushMvaAsid(Addr mva, uint64_t asn);
138
139 /** Remove any entries that match the asn
140 * @param asn contextid/asn to flush on match
141 */
142 void flushAsid(uint64_t asn);
143
144 /** Remove all entries that match the va regardless of asn
145 * @param mva address to flush from cache
146 */
147 void flushMva(Addr mva);
148
149 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
150 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
151 bool is_write, uint8_t domain, bool sNp);
152
153 void printTlb();
154
155 void demapPage(Addr vaddr, uint64_t asn)
156 {
157 flushMvaAsid(vaddr, asn);
158 }
159
160 static bool validVirtualAddress(Addr vaddr);
161
162 /**
163 * Do a functional lookup on the TLB (for debugging)
164 * and don't modify any internal state
165 * @param tc thread context to get the context id from
166 * @param vaddr virtual address to translate
167 * @param pa returned physical address
168 * @return if the translation was successful
169 */
170 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
171
172 /** Accessor functions for memory attributes for last accessed TLB entry
173 */
174 void
175 setAttr(uint32_t attr)
176 {
177 _attr = attr;
178 }
179 uint32_t
180 getAttr() const
181 {
182 return _attr;
183 }
184
185#if FULL_SYSTEM
186 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
187 Translation *translation, bool &delay, bool timing);
188#else
189 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
190 Translation *translation, bool &delay, bool timing);
191#endif
192 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
193 Fault translateTiming(RequestPtr req, ThreadContext *tc,
194 Translation *translation, Mode mode);
195
196 // Checkpointing
197 void serialize(std::ostream &os);
198 void unserialize(Checkpoint *cp, const std::string §ion);
199
200 void regStats();
201};
202
203/* namespace ArmISA */ }
204
205#endif // __ARCH_ARM_TLB_HH__
|