1/*
| 1/*
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| 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 *
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2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
| 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
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3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * Copyright (c) 2007-2008 The Florida State University
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5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer; 11 * redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution; 14 * neither the name of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 *
| 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 *
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30 * Authors: Nathan Binkert 31 * Steve Reinhardt 32 * Stephen Hines
| 40 * Authors: Ali Saidi
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33 */ 34 35#ifndef __ARCH_ARM_TLB_HH__ 36#define __ARCH_ARM_TLB_HH__ 37 38#include <map> 39 40#include "arch/arm/isa_traits.hh" 41#include "arch/arm/utility.hh" 42#include "arch/arm/vtophys.hh" 43#include "arch/arm/pagetable.hh" 44#include "base/statistics.hh" 45#include "mem/request.hh" 46#include "params/ArmTLB.hh" 47#include "sim/faults.hh" 48#include "sim/tlb.hh" 49 50class ThreadContext; 51
| 41 */ 42 43#ifndef __ARCH_ARM_TLB_HH__ 44#define __ARCH_ARM_TLB_HH__ 45 46#include <map> 47 48#include "arch/arm/isa_traits.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/vtophys.hh" 51#include "arch/arm/pagetable.hh" 52#include "base/statistics.hh" 53#include "mem/request.hh" 54#include "params/ArmTLB.hh" 55#include "sim/faults.hh" 56#include "sim/tlb.hh" 57 58class ThreadContext; 59
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52/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB 53 However, to maintain compatibility with other architectures, we'll 54 simply create an ITLB and DTLB that will point to the real TLB */
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55namespace ArmISA { 56
| 60namespace ArmISA { 61
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57// WARN: This particular TLB entry is not necessarily conformed to ARM ISA 58struct TlbEntry 59{ 60 Addr _pageStart; 61 TlbEntry() {} 62 TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {} 63 64 void 65 updateVaddr(Addr new_vaddr) 66 { 67 panic("unimplemented"); 68 } 69 70 Addr pageStart() 71 { 72 return _pageStart; 73 } 74 75 void serialize(std::ostream &os) 76 { 77 SERIALIZE_SCALAR(_pageStart); 78 } 79 80 void unserialize(Checkpoint *cp, const std::string §ion) 81 { 82 UNSERIALIZE_SCALAR(_pageStart); 83 } 84 85}; 86
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87class TLB : public BaseTLB 88{ 89 public: 90 enum ArmFlags { 91 AlignmentMask = 0x7, 92 93 AlignByte = 0x0, 94 AlignHalfWord = 0x1, 95 AlignWord = 0x3, 96 AlignDoubleWord = 0x7, 97 98 AllowUnaligned = 0x8, 99 // Because zero otherwise looks like a valid setting and may be used 100 // accidentally, this bit must be non-zero to show it was used on 101 // purpose. 102 MustBeOne = 0x10 103 }; 104 protected: 105 typedef std::multimap<Addr, int> PageTable; 106 PageTable lookupTable; // Quick lookup into page table 107 108 ArmISA::PTE *table; // the Page Table 109 int size; // TLB Size 110 int nlu; // not last used entry (for replacement) 111 112 void nextnlu() { if (++nlu >= size) nlu = 0; } 113 ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const; 114
| 62class TLB : public BaseTLB 63{ 64 public: 65 enum ArmFlags { 66 AlignmentMask = 0x7, 67 68 AlignByte = 0x0, 69 AlignHalfWord = 0x1, 70 AlignWord = 0x3, 71 AlignDoubleWord = 0x7, 72 73 AllowUnaligned = 0x8, 74 // Because zero otherwise looks like a valid setting and may be used 75 // accidentally, this bit must be non-zero to show it was used on 76 // purpose. 77 MustBeOne = 0x10 78 }; 79 protected: 80 typedef std::multimap<Addr, int> PageTable; 81 PageTable lookupTable; // Quick lookup into page table 82 83 ArmISA::PTE *table; // the Page Table 84 int size; // TLB Size 85 int nlu; // not last used entry (for replacement) 86 87 void nextnlu() { if (++nlu >= size) nlu = 0; } 88 ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const; 89
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| 90 // Access Stats
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115 mutable Stats::Scalar read_hits; 116 mutable Stats::Scalar read_misses; 117 mutable Stats::Scalar read_acv; 118 mutable Stats::Scalar read_accesses; 119 mutable Stats::Scalar write_hits; 120 mutable Stats::Scalar write_misses; 121 mutable Stats::Scalar write_acv; 122 mutable Stats::Scalar write_accesses; 123 Stats::Formula hits; 124 Stats::Formula misses; 125 Stats::Formula invalids; 126 Stats::Formula accesses; 127 128 public: 129 typedef ArmTLBParams Params; 130 TLB(const Params *p); 131
| 91 mutable Stats::Scalar read_hits; 92 mutable Stats::Scalar read_misses; 93 mutable Stats::Scalar read_acv; 94 mutable Stats::Scalar read_accesses; 95 mutable Stats::Scalar write_hits; 96 mutable Stats::Scalar write_misses; 97 mutable Stats::Scalar write_acv; 98 mutable Stats::Scalar write_accesses; 99 Stats::Formula hits; 100 Stats::Formula misses; 101 Stats::Formula invalids; 102 Stats::Formula accesses; 103 104 public: 105 typedef ArmTLBParams Params; 106 TLB(const Params *p); 107
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132 int probeEntry(Addr vpn,uint8_t) const; 133 ArmISA::PTE *getEntry(unsigned) const;
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134 virtual ~TLB();
| 108 virtual ~TLB();
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135 int smallPages;
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136 int getsize() const { return size; } 137
| 109 int getsize() const { return size; } 110
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138 ArmISA::PTE &index(bool advance = true);
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139 void insert(Addr vaddr, ArmISA::PTE &pte);
| 111 void insert(Addr vaddr, ArmISA::PTE &pte);
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140 void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages);
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141 void flushAll(); 142 void demapPage(Addr vaddr, uint64_t asn) 143 { 144 panic("demapPage unimplemented.\n"); 145 } 146
| 112 void flushAll(); 113 void demapPage(Addr vaddr, uint64_t asn) 114 { 115 panic("demapPage unimplemented.\n"); 116 } 117
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147 // static helper functions... really
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148 static bool validVirtualAddress(Addr vaddr); 149
| 118 static bool validVirtualAddress(Addr vaddr); 119
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150 static Fault checkCacheability(RequestPtr &req); 151
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152 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 153 void translateTiming(RequestPtr req, ThreadContext *tc, 154 Translation *translation, Mode mode); 155 156 // Checkpointing 157 void serialize(std::ostream &os); 158 void unserialize(Checkpoint *cp, const std::string §ion); 159 160 void regStats(); 161}; 162 163/* namespace ArmISA */ } 164 165#endif // __ARCH_ARM_TLB_HH__
| 120 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 121 void translateTiming(RequestPtr req, ThreadContext *tc, 122 Translation *translation, Mode mode); 123 124 // Checkpointing 125 void serialize(std::ostream &os); 126 void unserialize(Checkpoint *cp, const std::string §ion); 127 128 void regStats(); 129}; 130 131/* namespace ArmISA */ } 132 133#endif // __ARCH_ARM_TLB_HH__
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