1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Nathan Binkert
31 * Steve Reinhardt
32 * Stephen Hines
33 */
34
35#ifndef __ARCH_ARM_TLB_HH__
36#define __ARCH_ARM_TLB_HH__
37
38#include <map>
39
40#include "arch/arm/isa_traits.hh"
41#include "arch/arm/utility.hh"
42#include "arch/arm/vtophys.hh"
43#include "arch/arm/pagetable.hh"
44#include "base/statistics.hh"
45#include "mem/request.hh"
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Nathan Binkert
31 * Steve Reinhardt
32 * Stephen Hines
33 */
34
35#ifndef __ARCH_ARM_TLB_HH__
36#define __ARCH_ARM_TLB_HH__
37
38#include <map>
39
40#include "arch/arm/isa_traits.hh"
41#include "arch/arm/utility.hh"
42#include "arch/arm/vtophys.hh"
43#include "arch/arm/pagetable.hh"
44#include "base/statistics.hh"
45#include "mem/request.hh"
|
46#include "params/ArmDTB.hh"
47#include "params/ArmITB.hh"
| 46#include "params/ArmTLB.hh"
|
48#include "sim/faults.hh"
49#include "sim/tlb.hh"
50
51class ThreadContext;
52
53/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB
54 However, to maintain compatibility with other architectures, we'll
55 simply create an ITLB and DTLB that will point to the real TLB */
56namespace ArmISA {
57
58// WARN: This particular TLB entry is not necessarily conformed to ARM ISA
59struct TlbEntry
60{
61 Addr _pageStart;
62 TlbEntry() {}
63 TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
64
65 void
66 updateVaddr(Addr new_vaddr)
67 {
68 panic("unimplemented");
69 }
70
71 Addr pageStart()
72 {
73 return _pageStart;
74 }
75
76 void serialize(std::ostream &os)
77 {
78 SERIALIZE_SCALAR(_pageStart);
79 }
80
81 void unserialize(Checkpoint *cp, const std::string §ion)
82 {
83 UNSERIALIZE_SCALAR(_pageStart);
84 }
85
86};
87
88class TLB : public BaseTLB
89{
90 protected:
91 typedef std::multimap<Addr, int> PageTable;
92 PageTable lookupTable; // Quick lookup into page table
93
94 ArmISA::PTE *table; // the Page Table
95 int size; // TLB Size
96 int nlu; // not last used entry (for replacement)
97
98 void nextnlu() { if (++nlu >= size) nlu = 0; }
99 ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
100
101 mutable Stats::Scalar read_hits;
102 mutable Stats::Scalar read_misses;
103 mutable Stats::Scalar read_acv;
104 mutable Stats::Scalar read_accesses;
105 mutable Stats::Scalar write_hits;
106 mutable Stats::Scalar write_misses;
107 mutable Stats::Scalar write_acv;
108 mutable Stats::Scalar write_accesses;
109 Stats::Formula hits;
110 Stats::Formula misses;
111 Stats::Formula invalids;
112 Stats::Formula accesses;
113
114 public:
115 typedef ArmTLBParams Params;
116 TLB(const Params *p);
117
118 int probeEntry(Addr vpn,uint8_t) const;
119 ArmISA::PTE *getEntry(unsigned) const;
120 virtual ~TLB();
121 int smallPages;
122 int getsize() const { return size; }
123
124 ArmISA::PTE &index(bool advance = true);
125 void insert(Addr vaddr, ArmISA::PTE &pte);
126 void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages);
127 void flushAll();
128 void demapPage(Addr vaddr, uint64_t asn)
129 {
130 panic("demapPage unimplemented.\n");
131 }
132
133 // static helper functions... really
134 static bool validVirtualAddress(Addr vaddr);
135
136 static Fault checkCacheability(RequestPtr &req);
137
| 47#include "sim/faults.hh"
48#include "sim/tlb.hh"
49
50class ThreadContext;
51
52/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB
53 However, to maintain compatibility with other architectures, we'll
54 simply create an ITLB and DTLB that will point to the real TLB */
55namespace ArmISA {
56
57// WARN: This particular TLB entry is not necessarily conformed to ARM ISA
58struct TlbEntry
59{
60 Addr _pageStart;
61 TlbEntry() {}
62 TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
63
64 void
65 updateVaddr(Addr new_vaddr)
66 {
67 panic("unimplemented");
68 }
69
70 Addr pageStart()
71 {
72 return _pageStart;
73 }
74
75 void serialize(std::ostream &os)
76 {
77 SERIALIZE_SCALAR(_pageStart);
78 }
79
80 void unserialize(Checkpoint *cp, const std::string §ion)
81 {
82 UNSERIALIZE_SCALAR(_pageStart);
83 }
84
85};
86
87class TLB : public BaseTLB
88{
89 protected:
90 typedef std::multimap<Addr, int> PageTable;
91 PageTable lookupTable; // Quick lookup into page table
92
93 ArmISA::PTE *table; // the Page Table
94 int size; // TLB Size
95 int nlu; // not last used entry (for replacement)
96
97 void nextnlu() { if (++nlu >= size) nlu = 0; }
98 ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
99
100 mutable Stats::Scalar read_hits;
101 mutable Stats::Scalar read_misses;
102 mutable Stats::Scalar read_acv;
103 mutable Stats::Scalar read_accesses;
104 mutable Stats::Scalar write_hits;
105 mutable Stats::Scalar write_misses;
106 mutable Stats::Scalar write_acv;
107 mutable Stats::Scalar write_accesses;
108 Stats::Formula hits;
109 Stats::Formula misses;
110 Stats::Formula invalids;
111 Stats::Formula accesses;
112
113 public:
114 typedef ArmTLBParams Params;
115 TLB(const Params *p);
116
117 int probeEntry(Addr vpn,uint8_t) const;
118 ArmISA::PTE *getEntry(unsigned) const;
119 virtual ~TLB();
120 int smallPages;
121 int getsize() const { return size; }
122
123 ArmISA::PTE &index(bool advance = true);
124 void insert(Addr vaddr, ArmISA::PTE &pte);
125 void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages);
126 void flushAll();
127 void demapPage(Addr vaddr, uint64_t asn)
128 {
129 panic("demapPage unimplemented.\n");
130 }
131
132 // static helper functions... really
133 static bool validVirtualAddress(Addr vaddr);
134
135 static Fault checkCacheability(RequestPtr &req);
136
|
| 137 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
138 void translateTiming(RequestPtr req, ThreadContext *tc,
139 Translation *translation, Mode mode);
140
|
138 // Checkpointing
139 void serialize(std::ostream &os);
140 void unserialize(Checkpoint *cp, const std::string §ion);
141
142 void regStats();
143};
144
| 141 // Checkpointing
142 void serialize(std::ostream &os);
143 void unserialize(Checkpoint *cp, const std::string §ion);
144
145 void regStats();
146};
147
|
145class ITB : public TLB
146{
147 public:
148 typedef ArmTLBParams Params;
149 ITB(const Params *p);
| 148/* namespace ArmISA */ }
|
150
| 149
|
151 Fault translateAtomic(RequestPtr req, ThreadContext *tc);
152 void translateTiming(RequestPtr req, ThreadContext *tc,
153 Translation *translation);
154};
155
156class DTB : public TLB
157{
158 public:
159 typedef ArmTLBParams Params;
160 DTB(const Params *p);
161
162 Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
163 void translateTiming(RequestPtr req, ThreadContext *tc,
164 Translation *translation, bool write);
165};
166
167class UTB : public ITB, public DTB
168{
169 public:
170 typedef ArmTLBParams Params;
171 UTB(const Params *p);
172
173};
174
175}
176
| |
177#endif // __ARCH_ARM_TLB_HH__
| 150#endif // __ARCH_ARM_TLB_HH__
|