1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_TLB_HH__ 44#define __ARCH_ARM_TLB_HH__ 45 46 47#include "arch/arm/isa_traits.hh" 48#include "arch/arm/pagetable.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/vtophys.hh" 51#include "arch/generic/tlb.hh" 52#include "base/statistics.hh" 53#include "mem/request.hh" 54#include "params/ArmTLB.hh" 55#include "sim/probe/pmu.hh" 56 57class ThreadContext; 58 59namespace ArmISA { 60 61class TableWalker; 62class Stage2LookUp; 63class Stage2MMU; 64class TLB; 65 66class TlbTestInterface 67{ 68 public: 69 TlbTestInterface() {} 70 virtual ~TlbTestInterface() {} 71 72 /** 73 * Check if a TLB translation should be forced to fail. 74 * 75 * @param req Request requiring a translation. 76 * @param is_priv Access from a privileged mode (i.e., not EL0) 77 * @param mode Access type 78 * @param domain Domain type 79 */
| 1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_TLB_HH__ 44#define __ARCH_ARM_TLB_HH__ 45 46 47#include "arch/arm/isa_traits.hh" 48#include "arch/arm/pagetable.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/vtophys.hh" 51#include "arch/generic/tlb.hh" 52#include "base/statistics.hh" 53#include "mem/request.hh" 54#include "params/ArmTLB.hh" 55#include "sim/probe/pmu.hh" 56 57class ThreadContext; 58 59namespace ArmISA { 60 61class TableWalker; 62class Stage2LookUp; 63class Stage2MMU; 64class TLB; 65 66class TlbTestInterface 67{ 68 public: 69 TlbTestInterface() {} 70 virtual ~TlbTestInterface() {} 71 72 /** 73 * Check if a TLB translation should be forced to fail. 74 * 75 * @param req Request requiring a translation. 76 * @param is_priv Access from a privileged mode (i.e., not EL0) 77 * @param mode Access type 78 * @param domain Domain type 79 */
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80 virtual Fault translationCheck(RequestPtr req, bool is_priv,
| 80 virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
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81 BaseTLB::Mode mode, 82 TlbEntry::DomainType domain) = 0; 83 84 /** 85 * Check if a page table walker access should be forced to fail. 86 * 87 * @param pa Physical address the walker is accessing 88 * @param size Walker access size 89 * @param va Virtual address that initiated the walk 90 * @param is_secure Access from secure state 91 * @param is_priv Access from a privileged mode (i.e., not EL0) 92 * @param mode Access type 93 * @param domain Domain type 94 * @param lookup_level Page table walker level 95 */ 96 virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure, 97 Addr is_priv, BaseTLB::Mode mode, 98 TlbEntry::DomainType domain, 99 LookupLevel lookup_level) = 0; 100}; 101 102class TLB : public BaseTLB 103{ 104 public: 105 enum ArmFlags { 106 AlignmentMask = 0x7, 107 108 AlignByte = 0x0, 109 AlignHalfWord = 0x1, 110 AlignWord = 0x2, 111 AlignDoubleWord = 0x3, 112 AlignQuadWord = 0x4, 113 AlignOctWord = 0x5, 114 115 AllowUnaligned = 0x8, 116 // Priv code operating as if it wasn't 117 UserMode = 0x10, 118 // Because zero otherwise looks like a valid setting and may be used 119 // accidentally, this bit must be non-zero to show it was used on 120 // purpose. 121 MustBeOne = 0x40 122 }; 123 124 enum ArmTranslationType { 125 NormalTran = 0, 126 S1CTran = 0x1, 127 HypMode = 0x2, 128 // Secure code operating as if it wasn't (required by some Address 129 // Translate operations) 130 S1S2NsTran = 0x4, 131 // Address translation instructions (eg AT S1E0R_Xt) need to be handled 132 // in special ways during translation because they could need to act 133 // like a different EL than the current EL. The following flags are 134 // for these instructions 135 S1E0Tran = 0x8, 136 S1E1Tran = 0x10, 137 S1E2Tran = 0x20, 138 S1E3Tran = 0x40, 139 S12E0Tran = 0x80, 140 S12E1Tran = 0x100 141 }; 142 143 /** 144 * Determine the EL to use for the purpose of a translation given 145 * a specific translation type. If the translation type doesn't 146 * specify an EL, we use the current EL. 147 */ 148 static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type); 149 150 protected: 151 TlbEntry* table; // the Page Table 152 int size; // TLB Size 153 bool isStage2; // Indicates this TLB is part of the second stage MMU 154 bool stage2Req; // Indicates whether a stage 2 lookup is also required 155 uint64_t _attr; // Memory attributes for last accessed TLB entry 156 bool directToStage2; // Indicates whether all translation requests should 157 // be routed directly to the stage 2 TLB 158 159 TableWalker *tableWalker; 160 TLB *stage2Tlb; 161 Stage2MMU *stage2Mmu; 162 163 TlbTestInterface *test; 164 165 // Access Stats 166 mutable Stats::Scalar instHits; 167 mutable Stats::Scalar instMisses; 168 mutable Stats::Scalar readHits; 169 mutable Stats::Scalar readMisses; 170 mutable Stats::Scalar writeHits; 171 mutable Stats::Scalar writeMisses; 172 mutable Stats::Scalar inserts; 173 mutable Stats::Scalar flushTlb; 174 mutable Stats::Scalar flushTlbMva; 175 mutable Stats::Scalar flushTlbMvaAsid; 176 mutable Stats::Scalar flushTlbAsid; 177 mutable Stats::Scalar flushedEntries; 178 mutable Stats::Scalar alignFaults; 179 mutable Stats::Scalar prefetchFaults; 180 mutable Stats::Scalar domainFaults; 181 mutable Stats::Scalar permsFaults; 182 183 Stats::Formula readAccesses; 184 Stats::Formula writeAccesses; 185 Stats::Formula instAccesses; 186 Stats::Formula hits; 187 Stats::Formula misses; 188 Stats::Formula accesses; 189 190 /** PMU probe for TLB refills */ 191 ProbePoints::PMUUPtr ppRefills; 192 193 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 194 195 public: 196 TLB(const ArmTLBParams *p); 197 TLB(const Params *p, int _size, TableWalker *_walker); 198 199 /** Lookup an entry in the TLB 200 * @param vpn virtual address 201 * @param asn context id/address space id to use 202 * @param vmid The virtual machine ID used for stage 2 translation 203 * @param secure if the lookup is secure 204 * @param hyp if the lookup is done from hyp mode 205 * @param functional if the lookup should modify state 206 * @param ignore_asn if on lookup asn should be ignored 207 * @return pointer to TLB entry if it exists 208 */ 209 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 210 bool secure, bool functional, 211 bool ignore_asn, uint8_t target_el); 212 213 virtual ~TLB(); 214 215 void takeOverFrom(BaseTLB *otlb) override; 216 217 /// setup all the back pointers 218 void init() override; 219 220 void setTestInterface(SimObject *ti); 221 222 TableWalker *getTableWalker() { return tableWalker; } 223 224 void setMMU(Stage2MMU *m, MasterID master_id); 225 226 int getsize() const { return size; } 227 228 void insert(Addr vaddr, TlbEntry &pte); 229
| 81 BaseTLB::Mode mode, 82 TlbEntry::DomainType domain) = 0; 83 84 /** 85 * Check if a page table walker access should be forced to fail. 86 * 87 * @param pa Physical address the walker is accessing 88 * @param size Walker access size 89 * @param va Virtual address that initiated the walk 90 * @param is_secure Access from secure state 91 * @param is_priv Access from a privileged mode (i.e., not EL0) 92 * @param mode Access type 93 * @param domain Domain type 94 * @param lookup_level Page table walker level 95 */ 96 virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure, 97 Addr is_priv, BaseTLB::Mode mode, 98 TlbEntry::DomainType domain, 99 LookupLevel lookup_level) = 0; 100}; 101 102class TLB : public BaseTLB 103{ 104 public: 105 enum ArmFlags { 106 AlignmentMask = 0x7, 107 108 AlignByte = 0x0, 109 AlignHalfWord = 0x1, 110 AlignWord = 0x2, 111 AlignDoubleWord = 0x3, 112 AlignQuadWord = 0x4, 113 AlignOctWord = 0x5, 114 115 AllowUnaligned = 0x8, 116 // Priv code operating as if it wasn't 117 UserMode = 0x10, 118 // Because zero otherwise looks like a valid setting and may be used 119 // accidentally, this bit must be non-zero to show it was used on 120 // purpose. 121 MustBeOne = 0x40 122 }; 123 124 enum ArmTranslationType { 125 NormalTran = 0, 126 S1CTran = 0x1, 127 HypMode = 0x2, 128 // Secure code operating as if it wasn't (required by some Address 129 // Translate operations) 130 S1S2NsTran = 0x4, 131 // Address translation instructions (eg AT S1E0R_Xt) need to be handled 132 // in special ways during translation because they could need to act 133 // like a different EL than the current EL. The following flags are 134 // for these instructions 135 S1E0Tran = 0x8, 136 S1E1Tran = 0x10, 137 S1E2Tran = 0x20, 138 S1E3Tran = 0x40, 139 S12E0Tran = 0x80, 140 S12E1Tran = 0x100 141 }; 142 143 /** 144 * Determine the EL to use for the purpose of a translation given 145 * a specific translation type. If the translation type doesn't 146 * specify an EL, we use the current EL. 147 */ 148 static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type); 149 150 protected: 151 TlbEntry* table; // the Page Table 152 int size; // TLB Size 153 bool isStage2; // Indicates this TLB is part of the second stage MMU 154 bool stage2Req; // Indicates whether a stage 2 lookup is also required 155 uint64_t _attr; // Memory attributes for last accessed TLB entry 156 bool directToStage2; // Indicates whether all translation requests should 157 // be routed directly to the stage 2 TLB 158 159 TableWalker *tableWalker; 160 TLB *stage2Tlb; 161 Stage2MMU *stage2Mmu; 162 163 TlbTestInterface *test; 164 165 // Access Stats 166 mutable Stats::Scalar instHits; 167 mutable Stats::Scalar instMisses; 168 mutable Stats::Scalar readHits; 169 mutable Stats::Scalar readMisses; 170 mutable Stats::Scalar writeHits; 171 mutable Stats::Scalar writeMisses; 172 mutable Stats::Scalar inserts; 173 mutable Stats::Scalar flushTlb; 174 mutable Stats::Scalar flushTlbMva; 175 mutable Stats::Scalar flushTlbMvaAsid; 176 mutable Stats::Scalar flushTlbAsid; 177 mutable Stats::Scalar flushedEntries; 178 mutable Stats::Scalar alignFaults; 179 mutable Stats::Scalar prefetchFaults; 180 mutable Stats::Scalar domainFaults; 181 mutable Stats::Scalar permsFaults; 182 183 Stats::Formula readAccesses; 184 Stats::Formula writeAccesses; 185 Stats::Formula instAccesses; 186 Stats::Formula hits; 187 Stats::Formula misses; 188 Stats::Formula accesses; 189 190 /** PMU probe for TLB refills */ 191 ProbePoints::PMUUPtr ppRefills; 192 193 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 194 195 public: 196 TLB(const ArmTLBParams *p); 197 TLB(const Params *p, int _size, TableWalker *_walker); 198 199 /** Lookup an entry in the TLB 200 * @param vpn virtual address 201 * @param asn context id/address space id to use 202 * @param vmid The virtual machine ID used for stage 2 translation 203 * @param secure if the lookup is secure 204 * @param hyp if the lookup is done from hyp mode 205 * @param functional if the lookup should modify state 206 * @param ignore_asn if on lookup asn should be ignored 207 * @return pointer to TLB entry if it exists 208 */ 209 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 210 bool secure, bool functional, 211 bool ignore_asn, uint8_t target_el); 212 213 virtual ~TLB(); 214 215 void takeOverFrom(BaseTLB *otlb) override; 216 217 /// setup all the back pointers 218 void init() override; 219 220 void setTestInterface(SimObject *ti); 221 222 TableWalker *getTableWalker() { return tableWalker; } 223 224 void setMMU(Stage2MMU *m, MasterID master_id); 225 226 int getsize() const { return size; } 227 228 void insert(Addr vaddr, TlbEntry &pte); 229
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230 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
| 230 Fault getTE(TlbEntry **te, const RequestPtr &req, 231 ThreadContext *tc, Mode mode,
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231 Translation *translation, bool timing, bool functional, 232 bool is_secure, ArmTranslationType tranType); 233
| 232 Translation *translation, bool timing, bool functional, 233 bool is_secure, ArmTranslationType tranType); 234
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234 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 235 Mode mode, Translation *translation, bool timing,
| 235 Fault getResultTe(TlbEntry **te, const RequestPtr &req, 236 ThreadContext *tc, Mode mode, 237 Translation *translation, bool timing,
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236 bool functional, TlbEntry *mergeTe); 237
| 238 bool functional, TlbEntry *mergeTe); 239
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238 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 239 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
| 240 Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode); 241 Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
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240 ThreadContext *tc); 241 242 243 /** Reset the entire TLB 244 * @param secure_lookup if the operation affects the secure world 245 */ 246 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 247 bool ignore_el = false); 248 249 /** Remove all entries in the non secure world, depending on whether they 250 * were allocated in hyp mode or not 251 * @param hyp if the opperation affects hyp mode 252 */ 253 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 254 255 256 /** Reset the entire TLB. Used for CPU switching to prevent stale 257 * translations after multiple switches 258 */ 259 void flushAll() override 260 { 261 flushAllSecurity(false, 0, true); 262 flushAllSecurity(true, 0, true); 263 } 264 265 /** Remove any entries that match both a va and asn 266 * @param mva virtual address to flush 267 * @param asn contextid/asn to flush on match 268 * @param secure_lookup if the operation affects the secure world 269 */ 270 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 271 uint8_t target_el); 272 273 /** Remove any entries that match the asn 274 * @param asn contextid/asn to flush on match 275 * @param secure_lookup if the operation affects the secure world 276 */ 277 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 278 279 /** Remove all entries that match the va regardless of asn 280 * @param mva address to flush from cache 281 * @param secure_lookup if the operation affects the secure world 282 * @param hyp if the operation affects hyp mode 283 */ 284 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 285 286 /** 287 * Invalidate all entries in the stage 2 TLB that match the given ipa 288 * and the current VMID 289 * @param ipa the address to invalidate 290 * @param secure_lookup if the operation affects the secure world 291 * @param hyp if the operation affects hyp mode 292 */ 293 void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el); 294
| 242 ThreadContext *tc); 243 244 245 /** Reset the entire TLB 246 * @param secure_lookup if the operation affects the secure world 247 */ 248 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 249 bool ignore_el = false); 250 251 /** Remove all entries in the non secure world, depending on whether they 252 * were allocated in hyp mode or not 253 * @param hyp if the opperation affects hyp mode 254 */ 255 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 256 257 258 /** Reset the entire TLB. Used for CPU switching to prevent stale 259 * translations after multiple switches 260 */ 261 void flushAll() override 262 { 263 flushAllSecurity(false, 0, true); 264 flushAllSecurity(true, 0, true); 265 } 266 267 /** Remove any entries that match both a va and asn 268 * @param mva virtual address to flush 269 * @param asn contextid/asn to flush on match 270 * @param secure_lookup if the operation affects the secure world 271 */ 272 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 273 uint8_t target_el); 274 275 /** Remove any entries that match the asn 276 * @param asn contextid/asn to flush on match 277 * @param secure_lookup if the operation affects the secure world 278 */ 279 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 280 281 /** Remove all entries that match the va regardless of asn 282 * @param mva address to flush from cache 283 * @param secure_lookup if the operation affects the secure world 284 * @param hyp if the operation affects hyp mode 285 */ 286 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 287 288 /** 289 * Invalidate all entries in the stage 2 TLB that match the given ipa 290 * and the current VMID 291 * @param ipa the address to invalidate 292 * @param secure_lookup if the operation affects the secure world 293 * @param hyp if the operation affects hyp mode 294 */ 295 void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el); 296
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295 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 296 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 297 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
| 297 Fault trickBoxCheck(const RequestPtr &req, Mode mode, 298 TlbEntry::DomainType domain);
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298
| 299
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| 300 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, 301 bool is_exec, bool is_write, 302 TlbEntry::DomainType domain, 303 LookupLevel lookup_level); 304
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299 void printTlb() const; 300 301 void demapPage(Addr vaddr, uint64_t asn) override 302 { 303 // needed for x86 only 304 panic("demapPage() is not implemented.\n"); 305 } 306 307 /** 308 * Do a functional lookup on the TLB (for debugging) 309 * and don't modify any internal state 310 * @param tc thread context to get the context id from 311 * @param vaddr virtual address to translate 312 * @param pa returned physical address 313 * @return if the translation was successful 314 */ 315 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 316 317 /** 318 * Do a functional lookup on the TLB (for checker cpu) that 319 * behaves like a normal lookup without modifying any page table state. 320 */
| 305 void printTlb() const; 306 307 void demapPage(Addr vaddr, uint64_t asn) override 308 { 309 // needed for x86 only 310 panic("demapPage() is not implemented.\n"); 311 } 312 313 /** 314 * Do a functional lookup on the TLB (for debugging) 315 * and don't modify any internal state 316 * @param tc thread context to get the context id from 317 * @param vaddr virtual address to translate 318 * @param pa returned physical address 319 * @return if the translation was successful 320 */ 321 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 322 323 /** 324 * Do a functional lookup on the TLB (for checker cpu) that 325 * behaves like a normal lookup without modifying any page table state. 326 */
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321 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 322 ArmTranslationType tranType);
| 327 Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, 328 Mode mode, ArmTranslationType tranType);
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323 Fault
| 329 Fault
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324 translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) override
| 330 translateFunctional(const RequestPtr &req, 331 ThreadContext *tc, Mode mode) override
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325 { 326 return translateFunctional(req, tc, mode, NormalTran); 327 } 328 329 /** Accessor functions for memory attributes for last accessed TLB entry 330 */ 331 void 332 setAttr(uint64_t attr) 333 { 334 _attr = attr; 335 } 336 337 uint64_t 338 getAttr() const 339 { 340 return _attr; 341 } 342
| 332 { 333 return translateFunctional(req, tc, mode, NormalTran); 334 } 335 336 /** Accessor functions for memory attributes for last accessed TLB entry 337 */ 338 void 339 setAttr(uint64_t attr) 340 { 341 _attr = attr; 342 } 343 344 uint64_t 345 getAttr() const 346 { 347 return _attr; 348 } 349
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343 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
| 350 Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
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344 Translation *translation, bool &delay, 345 bool timing, ArmTranslationType tranType, bool functional = false);
| 351 Translation *translation, bool &delay, 352 bool timing, ArmTranslationType tranType, bool functional = false);
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346 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
| 353 Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
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347 Translation *translation, bool &delay, bool timing);
| 354 Translation *translation, bool &delay, bool timing);
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348 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
| 355 Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
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349 ArmTranslationType tranType); 350 Fault
| 356 ArmTranslationType tranType); 357 Fault
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351 translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) override
| 358 translateAtomic(const RequestPtr &req, 359 ThreadContext *tc, Mode mode) override
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352 { 353 return translateAtomic(req, tc, mode, NormalTran); 354 } 355 void translateTiming(
| 360 { 361 return translateAtomic(req, tc, mode, NormalTran); 362 } 363 void translateTiming(
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356 RequestPtr req, ThreadContext *tc,
| 364 const RequestPtr &req, ThreadContext *tc,
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357 Translation *translation, Mode mode, 358 ArmTranslationType tranType); 359 void
| 365 Translation *translation, Mode mode, 366 ArmTranslationType tranType); 367 void
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360 translateTiming(RequestPtr req, ThreadContext *tc,
| 368 translateTiming(const RequestPtr &req, ThreadContext *tc,
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361 Translation *translation, Mode mode) override 362 { 363 translateTiming(req, tc, translation, mode, NormalTran); 364 }
| 369 Translation *translation, Mode mode) override 370 { 371 translateTiming(req, tc, translation, mode, NormalTran); 372 }
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365 Fault translateComplete(RequestPtr req, ThreadContext *tc,
| 373 Fault translateComplete(const RequestPtr &req, ThreadContext *tc,
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366 Translation *translation, Mode mode, ArmTranslationType tranType, 367 bool callFromS2); 368 Fault finalizePhysical(
| 374 Translation *translation, Mode mode, ArmTranslationType tranType, 375 bool callFromS2); 376 Fault finalizePhysical(
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369 RequestPtr req, ThreadContext *tc, Mode mode) const override;
| 377 const RequestPtr &req, 378 ThreadContext *tc, Mode mode) const override;
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370 371 void drainResume() override; 372 373 // Checkpointing 374 void serialize(CheckpointOut &cp) const override; 375 void unserialize(CheckpointIn &cp) override; 376 377 void regStats() override; 378 379 void regProbePoints() override; 380 381 /** 382 * Get the table walker master port. This is used for migrating 383 * port connections during a CPU takeOverFrom() call. For 384 * architectures that do not have a table walker, NULL is 385 * returned, hence the use of a pointer rather than a 386 * reference. For ARM this method will always return a valid port 387 * pointer. 388 * 389 * @return A pointer to the walker master port 390 */ 391 BaseMasterPort* getMasterPort() override; 392 393 // Caching misc register values here. 394 // Writing to misc registers needs to invalidate them. 395 // translateFunctional/translateSe/translateFs checks if they are 396 // invalid and call updateMiscReg if necessary. 397protected: 398 CPSR cpsr; 399 bool aarch64; 400 ExceptionLevel aarch64EL; 401 SCTLR sctlr; 402 SCR scr; 403 bool isPriv; 404 bool isSecure; 405 bool isHyp; 406 TTBCR ttbcr; 407 uint16_t asid; 408 uint8_t vmid; 409 PRRR prrr; 410 NMRR nmrr; 411 HCR hcr; 412 uint32_t dacr; 413 bool miscRegValid; 414 ContextID miscRegContext; 415 ArmTranslationType curTranType; 416 417 // Cached copies of system-level properties 418 bool haveLPAE; 419 bool haveVirtualization; 420 bool haveLargeAsid64; 421 422 AddrRange m5opRange; 423 424 void updateMiscReg(ThreadContext *tc, 425 ArmTranslationType tranType = NormalTran); 426 427public: 428 const Params * 429 params() const 430 { 431 return dynamic_cast<const Params *>(_params); 432 } 433 inline void invalidateMiscReg() { miscRegValid = false; } 434 435private: 436 /** Remove any entries that match both a va and asn 437 * @param mva virtual address to flush 438 * @param asn contextid/asn to flush on match 439 * @param secure_lookup if the operation affects the secure world 440 * @param hyp if the operation affects hyp mode 441 * @param ignore_asn if the flush should ignore the asn 442 */ 443 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 444 bool hyp, bool ignore_asn, uint8_t target_el); 445 446 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 447 448 public: /* Testing */
| 379 380 void drainResume() override; 381 382 // Checkpointing 383 void serialize(CheckpointOut &cp) const override; 384 void unserialize(CheckpointIn &cp) override; 385 386 void regStats() override; 387 388 void regProbePoints() override; 389 390 /** 391 * Get the table walker master port. This is used for migrating 392 * port connections during a CPU takeOverFrom() call. For 393 * architectures that do not have a table walker, NULL is 394 * returned, hence the use of a pointer rather than a 395 * reference. For ARM this method will always return a valid port 396 * pointer. 397 * 398 * @return A pointer to the walker master port 399 */ 400 BaseMasterPort* getMasterPort() override; 401 402 // Caching misc register values here. 403 // Writing to misc registers needs to invalidate them. 404 // translateFunctional/translateSe/translateFs checks if they are 405 // invalid and call updateMiscReg if necessary. 406protected: 407 CPSR cpsr; 408 bool aarch64; 409 ExceptionLevel aarch64EL; 410 SCTLR sctlr; 411 SCR scr; 412 bool isPriv; 413 bool isSecure; 414 bool isHyp; 415 TTBCR ttbcr; 416 uint16_t asid; 417 uint8_t vmid; 418 PRRR prrr; 419 NMRR nmrr; 420 HCR hcr; 421 uint32_t dacr; 422 bool miscRegValid; 423 ContextID miscRegContext; 424 ArmTranslationType curTranType; 425 426 // Cached copies of system-level properties 427 bool haveLPAE; 428 bool haveVirtualization; 429 bool haveLargeAsid64; 430 431 AddrRange m5opRange; 432 433 void updateMiscReg(ThreadContext *tc, 434 ArmTranslationType tranType = NormalTran); 435 436public: 437 const Params * 438 params() const 439 { 440 return dynamic_cast<const Params *>(_params); 441 } 442 inline void invalidateMiscReg() { miscRegValid = false; } 443 444private: 445 /** Remove any entries that match both a va and asn 446 * @param mva virtual address to flush 447 * @param asn contextid/asn to flush on match 448 * @param secure_lookup if the operation affects the secure world 449 * @param hyp if the operation affects hyp mode 450 * @param ignore_asn if the flush should ignore the asn 451 */ 452 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 453 bool hyp, bool ignore_asn, uint8_t target_el); 454 455 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 456 457 public: /* Testing */
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449 Fault testTranslation(RequestPtr req, Mode mode,
| 458 Fault testTranslation(const RequestPtr &req, Mode mode,
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450 TlbEntry::DomainType domain); 451 Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 452 TlbEntry::DomainType domain, 453 LookupLevel lookup_level); 454}; 455 456template<typename T> 457TLB * 458getITBPtr(T *tc) 459{ 460 auto tlb = static_cast<TLB *>(tc->getITBPtr()); 461 assert(tlb); 462 return tlb; 463} 464 465template<typename T> 466TLB * 467getDTBPtr(T *tc) 468{ 469 auto tlb = static_cast<TLB *>(tc->getDTBPtr()); 470 assert(tlb); 471 return tlb; 472} 473 474} // namespace ArmISA 475 476#endif // __ARCH_ARM_TLB_HH__
| 459 TlbEntry::DomainType domain); 460 Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 461 TlbEntry::DomainType domain, 462 LookupLevel lookup_level); 463}; 464 465template<typename T> 466TLB * 467getITBPtr(T *tc) 468{ 469 auto tlb = static_cast<TLB *>(tc->getITBPtr()); 470 assert(tlb); 471 return tlb; 472} 473 474template<typename T> 475TLB * 476getDTBPtr(T *tc) 477{ 478 auto tlb = static_cast<TLB *>(tc->getDTBPtr()); 479 assert(tlb); 480 return tlb; 481} 482 483} // namespace ArmISA 484 485#endif // __ARCH_ARM_TLB_HH__
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