1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/pagetable.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/generic/tlb.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/probe/pmu.hh"
56
57class ThreadContext;
58
59namespace ArmISA {
60
61class TableWalker;
62class Stage2LookUp;
63class Stage2MMU;
| 1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/pagetable.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/generic/tlb.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/probe/pmu.hh"
56
57class ThreadContext;
58
59namespace ArmISA {
60
61class TableWalker;
62class Stage2LookUp;
63class Stage2MMU;
|
| 64class TLB;
|
64
| 65
|
| 66class TlbTestInterface
67{
68 public:
69 TlbTestInterface() {}
70 virtual ~TlbTestInterface() {}
71
72 /**
73 * Check if a TLB translation should be forced to fail.
74 *
75 * @param req Request requiring a translation.
76 * @param is_priv Access from a privileged mode (i.e., not EL0)
77 * @param mode Access type
78 * @param domain Domain type
79 */
80 virtual Fault translationCheck(RequestPtr req, bool is_priv,
81 BaseTLB::Mode mode,
82 TlbEntry::DomainType domain) = 0;
83
84 /**
85 * Check if a page table walker access should be forced to fail.
86 *
87 * @param pa Physical address the walker is accessing
88 * @param size Walker access size
89 * @param va Virtual address that initiated the walk
90 * @param is_secure Access from secure state
91 * @param is_priv Access from a privileged mode (i.e., not EL0)
92 * @param mode Access type
93 * @param domain Domain type
94 * @param lookup_level Page table walker level
95 */
96 virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
97 Addr is_priv, BaseTLB::Mode mode,
98 TlbEntry::DomainType domain,
99 LookupLevel lookup_level) = 0;
100};
101
|
65class TLB : public BaseTLB
66{
67 public:
68 enum ArmFlags {
69 AlignmentMask = 0x7,
70
71 AlignByte = 0x0,
72 AlignHalfWord = 0x1,
73 AlignWord = 0x2,
74 AlignDoubleWord = 0x3,
75 AlignQuadWord = 0x4,
76 AlignOctWord = 0x5,
77
78 AllowUnaligned = 0x8,
79 // Priv code operating as if it wasn't
80 UserMode = 0x10,
81 // Because zero otherwise looks like a valid setting and may be used
82 // accidentally, this bit must be non-zero to show it was used on
83 // purpose.
84 MustBeOne = 0x40
85 };
86
87 enum ArmTranslationType {
88 NormalTran = 0,
89 S1CTran = 0x1,
90 HypMode = 0x2,
91 // Secure code operating as if it wasn't (required by some Address
92 // Translate operations)
93 S1S2NsTran = 0x4
94 };
95 protected:
96 TlbEntry* table; // the Page Table
97 int size; // TLB Size
98 bool isStage2; // Indicates this TLB is part of the second stage MMU
99 bool stage2Req; // Indicates whether a stage 2 lookup is also required
100 uint64_t _attr; // Memory attributes for last accessed TLB entry
101 bool directToStage2; // Indicates whether all translation requests should
102 // be routed directly to the stage 2 TLB
103
104 TableWalker *tableWalker;
105 TLB *stage2Tlb;
106 Stage2MMU *stage2Mmu;
107
| 102class TLB : public BaseTLB
103{
104 public:
105 enum ArmFlags {
106 AlignmentMask = 0x7,
107
108 AlignByte = 0x0,
109 AlignHalfWord = 0x1,
110 AlignWord = 0x2,
111 AlignDoubleWord = 0x3,
112 AlignQuadWord = 0x4,
113 AlignOctWord = 0x5,
114
115 AllowUnaligned = 0x8,
116 // Priv code operating as if it wasn't
117 UserMode = 0x10,
118 // Because zero otherwise looks like a valid setting and may be used
119 // accidentally, this bit must be non-zero to show it was used on
120 // purpose.
121 MustBeOne = 0x40
122 };
123
124 enum ArmTranslationType {
125 NormalTran = 0,
126 S1CTran = 0x1,
127 HypMode = 0x2,
128 // Secure code operating as if it wasn't (required by some Address
129 // Translate operations)
130 S1S2NsTran = 0x4
131 };
132 protected:
133 TlbEntry* table; // the Page Table
134 int size; // TLB Size
135 bool isStage2; // Indicates this TLB is part of the second stage MMU
136 bool stage2Req; // Indicates whether a stage 2 lookup is also required
137 uint64_t _attr; // Memory attributes for last accessed TLB entry
138 bool directToStage2; // Indicates whether all translation requests should
139 // be routed directly to the stage 2 TLB
140
141 TableWalker *tableWalker;
142 TLB *stage2Tlb;
143 Stage2MMU *stage2Mmu;
144
|
| 145 TlbTestInterface *test;
146
|
108 // Access Stats
109 mutable Stats::Scalar instHits;
110 mutable Stats::Scalar instMisses;
111 mutable Stats::Scalar readHits;
112 mutable Stats::Scalar readMisses;
113 mutable Stats::Scalar writeHits;
114 mutable Stats::Scalar writeMisses;
115 mutable Stats::Scalar inserts;
116 mutable Stats::Scalar flushTlb;
117 mutable Stats::Scalar flushTlbMva;
118 mutable Stats::Scalar flushTlbMvaAsid;
119 mutable Stats::Scalar flushTlbAsid;
120 mutable Stats::Scalar flushedEntries;
121 mutable Stats::Scalar alignFaults;
122 mutable Stats::Scalar prefetchFaults;
123 mutable Stats::Scalar domainFaults;
124 mutable Stats::Scalar permsFaults;
125
126 Stats::Formula readAccesses;
127 Stats::Formula writeAccesses;
128 Stats::Formula instAccesses;
129 Stats::Formula hits;
130 Stats::Formula misses;
131 Stats::Formula accesses;
132
133 /** PMU probe for TLB refills */
134 ProbePoints::PMUUPtr ppRefills;
135
136 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
137
138 public:
139 TLB(const ArmTLBParams *p);
140 TLB(const Params *p, int _size, TableWalker *_walker);
141
142 /** Lookup an entry in the TLB
143 * @param vpn virtual address
144 * @param asn context id/address space id to use
145 * @param vmid The virtual machine ID used for stage 2 translation
146 * @param secure if the lookup is secure
147 * @param hyp if the lookup is done from hyp mode
148 * @param functional if the lookup should modify state
149 * @param ignore_asn if on lookup asn should be ignored
150 * @return pointer to TLB entry if it exists
151 */
152 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
153 bool secure, bool functional,
154 bool ignore_asn, uint8_t target_el);
155
156 virtual ~TLB();
157
158 void takeOverFrom(BaseTLB *otlb) override;
159
160 /// setup all the back pointers
161 void init() override;
162
| 147 // Access Stats
148 mutable Stats::Scalar instHits;
149 mutable Stats::Scalar instMisses;
150 mutable Stats::Scalar readHits;
151 mutable Stats::Scalar readMisses;
152 mutable Stats::Scalar writeHits;
153 mutable Stats::Scalar writeMisses;
154 mutable Stats::Scalar inserts;
155 mutable Stats::Scalar flushTlb;
156 mutable Stats::Scalar flushTlbMva;
157 mutable Stats::Scalar flushTlbMvaAsid;
158 mutable Stats::Scalar flushTlbAsid;
159 mutable Stats::Scalar flushedEntries;
160 mutable Stats::Scalar alignFaults;
161 mutable Stats::Scalar prefetchFaults;
162 mutable Stats::Scalar domainFaults;
163 mutable Stats::Scalar permsFaults;
164
165 Stats::Formula readAccesses;
166 Stats::Formula writeAccesses;
167 Stats::Formula instAccesses;
168 Stats::Formula hits;
169 Stats::Formula misses;
170 Stats::Formula accesses;
171
172 /** PMU probe for TLB refills */
173 ProbePoints::PMUUPtr ppRefills;
174
175 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
176
177 public:
178 TLB(const ArmTLBParams *p);
179 TLB(const Params *p, int _size, TableWalker *_walker);
180
181 /** Lookup an entry in the TLB
182 * @param vpn virtual address
183 * @param asn context id/address space id to use
184 * @param vmid The virtual machine ID used for stage 2 translation
185 * @param secure if the lookup is secure
186 * @param hyp if the lookup is done from hyp mode
187 * @param functional if the lookup should modify state
188 * @param ignore_asn if on lookup asn should be ignored
189 * @return pointer to TLB entry if it exists
190 */
191 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
192 bool secure, bool functional,
193 bool ignore_asn, uint8_t target_el);
194
195 virtual ~TLB();
196
197 void takeOverFrom(BaseTLB *otlb) override;
198
199 /// setup all the back pointers
200 void init() override;
201
|
| 202 void setTestInterface(SimObject *ti);
203
|
163 TableWalker *getTableWalker() { return tableWalker; }
164
165 void setMMU(Stage2MMU *m, MasterID master_id);
166
167 int getsize() const { return size; }
168
169 void insert(Addr vaddr, TlbEntry &pte);
170
171 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
172 Translation *translation, bool timing, bool functional,
173 bool is_secure, ArmTranslationType tranType);
174
175 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
176 Mode mode, Translation *translation, bool timing,
177 bool functional, TlbEntry *mergeTe);
178
179 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
180 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
181 ThreadContext *tc);
182
183
184 /** Reset the entire TLB
185 * @param secure_lookup if the operation affects the secure world
186 */
187 void flushAllSecurity(bool secure_lookup, uint8_t target_el,
188 bool ignore_el = false);
189
190 /** Remove all entries in the non secure world, depending on whether they
191 * were allocated in hyp mode or not
192 * @param hyp if the opperation affects hyp mode
193 */
194 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
195
196
197 /** Reset the entire TLB. Used for CPU switching to prevent stale
198 * translations after multiple switches
199 */
200 void flushAll() override
201 {
202 flushAllSecurity(false, 0, true);
203 flushAllSecurity(true, 0, true);
204 }
205
206 /** Remove any entries that match both a va and asn
207 * @param mva virtual address to flush
208 * @param asn contextid/asn to flush on match
209 * @param secure_lookup if the operation affects the secure world
210 */
211 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
212 uint8_t target_el);
213
214 /** Remove any entries that match the asn
215 * @param asn contextid/asn to flush on match
216 * @param secure_lookup if the operation affects the secure world
217 */
218 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
219
220 /** Remove all entries that match the va regardless of asn
221 * @param mva address to flush from cache
222 * @param secure_lookup if the operation affects the secure world
223 * @param hyp if the operation affects hyp mode
224 */
225 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
226
| 204 TableWalker *getTableWalker() { return tableWalker; }
205
206 void setMMU(Stage2MMU *m, MasterID master_id);
207
208 int getsize() const { return size; }
209
210 void insert(Addr vaddr, TlbEntry &pte);
211
212 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
213 Translation *translation, bool timing, bool functional,
214 bool is_secure, ArmTranslationType tranType);
215
216 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
217 Mode mode, Translation *translation, bool timing,
218 bool functional, TlbEntry *mergeTe);
219
220 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
221 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
222 ThreadContext *tc);
223
224
225 /** Reset the entire TLB
226 * @param secure_lookup if the operation affects the secure world
227 */
228 void flushAllSecurity(bool secure_lookup, uint8_t target_el,
229 bool ignore_el = false);
230
231 /** Remove all entries in the non secure world, depending on whether they
232 * were allocated in hyp mode or not
233 * @param hyp if the opperation affects hyp mode
234 */
235 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
236
237
238 /** Reset the entire TLB. Used for CPU switching to prevent stale
239 * translations after multiple switches
240 */
241 void flushAll() override
242 {
243 flushAllSecurity(false, 0, true);
244 flushAllSecurity(true, 0, true);
245 }
246
247 /** Remove any entries that match both a va and asn
248 * @param mva virtual address to flush
249 * @param asn contextid/asn to flush on match
250 * @param secure_lookup if the operation affects the secure world
251 */
252 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
253 uint8_t target_el);
254
255 /** Remove any entries that match the asn
256 * @param asn contextid/asn to flush on match
257 * @param secure_lookup if the operation affects the secure world
258 */
259 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
260
261 /** Remove all entries that match the va regardless of asn
262 * @param mva address to flush from cache
263 * @param secure_lookup if the operation affects the secure world
264 * @param hyp if the operation affects hyp mode
265 */
266 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
267
|
227 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
228 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
229 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
230
| |
231 void printTlb() const;
232
233 void demapPage(Addr vaddr, uint64_t asn) override
234 {
235 // needed for x86 only
236 panic("demapPage() is not implemented.\n");
237 }
238
239 /**
240 * Do a functional lookup on the TLB (for debugging)
241 * and don't modify any internal state
242 * @param tc thread context to get the context id from
243 * @param vaddr virtual address to translate
244 * @param pa returned physical address
245 * @return if the translation was successful
246 */
247 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
248
249 /**
250 * Do a functional lookup on the TLB (for checker cpu) that
251 * behaves like a normal lookup without modifying any page table state.
252 */
253 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
254 ArmTranslationType tranType = NormalTran);
255
256 /** Accessor functions for memory attributes for last accessed TLB entry
257 */
258 void
259 setAttr(uint64_t attr)
260 {
261 _attr = attr;
262 }
263
264 uint64_t
265 getAttr() const
266 {
267 return _attr;
268 }
269
270 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
271 Translation *translation, bool &delay,
272 bool timing, ArmTranslationType tranType, bool functional = false);
273 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
274 Translation *translation, bool &delay, bool timing);
275 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
276 ArmTranslationType tranType = NormalTran);
277 Fault translateTiming(RequestPtr req, ThreadContext *tc,
278 Translation *translation, Mode mode,
279 ArmTranslationType tranType = NormalTran);
280 Fault translateComplete(RequestPtr req, ThreadContext *tc,
281 Translation *translation, Mode mode, ArmTranslationType tranType,
282 bool callFromS2);
283 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
284
285 void drainResume() override;
286
287 // Checkpointing
288 void serialize(CheckpointOut &cp) const override;
289 void unserialize(CheckpointIn &cp) override;
290
291 void regStats() override;
292
293 void regProbePoints() override;
294
295 /**
296 * Get the table walker master port. This is used for migrating
297 * port connections during a CPU takeOverFrom() call. For
298 * architectures that do not have a table walker, NULL is
299 * returned, hence the use of a pointer rather than a
300 * reference. For ARM this method will always return a valid port
301 * pointer.
302 *
303 * @return A pointer to the walker master port
304 */
305 BaseMasterPort* getMasterPort() override;
306
307 // Caching misc register values here.
308 // Writing to misc registers needs to invalidate them.
309 // translateFunctional/translateSe/translateFs checks if they are
310 // invalid and call updateMiscReg if necessary.
311protected:
312 CPSR cpsr;
313 bool aarch64;
314 ExceptionLevel aarch64EL;
315 SCTLR sctlr;
316 SCR scr;
317 bool isPriv;
318 bool isSecure;
319 bool isHyp;
320 TTBCR ttbcr;
321 uint16_t asid;
322 uint8_t vmid;
323 PRRR prrr;
324 NMRR nmrr;
325 HCR hcr;
326 uint32_t dacr;
327 bool miscRegValid;
328 ContextID miscRegContext;
329 ArmTranslationType curTranType;
330
331 // Cached copies of system-level properties
332 bool haveLPAE;
333 bool haveVirtualization;
334 bool haveLargeAsid64;
335
336 void updateMiscReg(ThreadContext *tc,
337 ArmTranslationType tranType = NormalTran);
338
339public:
340 const Params *
341 params() const
342 {
343 return dynamic_cast<const Params *>(_params);
344 }
345 inline void invalidateMiscReg() { miscRegValid = false; }
346
347private:
348 /** Remove any entries that match both a va and asn
349 * @param mva virtual address to flush
350 * @param asn contextid/asn to flush on match
351 * @param secure_lookup if the operation affects the secure world
352 * @param hyp if the operation affects hyp mode
353 * @param ignore_asn if the flush should ignore the asn
354 */
355 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
356 bool hyp, bool ignore_asn, uint8_t target_el);
357
358 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
| 268 void printTlb() const;
269
270 void demapPage(Addr vaddr, uint64_t asn) override
271 {
272 // needed for x86 only
273 panic("demapPage() is not implemented.\n");
274 }
275
276 /**
277 * Do a functional lookup on the TLB (for debugging)
278 * and don't modify any internal state
279 * @param tc thread context to get the context id from
280 * @param vaddr virtual address to translate
281 * @param pa returned physical address
282 * @return if the translation was successful
283 */
284 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
285
286 /**
287 * Do a functional lookup on the TLB (for checker cpu) that
288 * behaves like a normal lookup without modifying any page table state.
289 */
290 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
291 ArmTranslationType tranType = NormalTran);
292
293 /** Accessor functions for memory attributes for last accessed TLB entry
294 */
295 void
296 setAttr(uint64_t attr)
297 {
298 _attr = attr;
299 }
300
301 uint64_t
302 getAttr() const
303 {
304 return _attr;
305 }
306
307 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
308 Translation *translation, bool &delay,
309 bool timing, ArmTranslationType tranType, bool functional = false);
310 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
311 Translation *translation, bool &delay, bool timing);
312 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
313 ArmTranslationType tranType = NormalTran);
314 Fault translateTiming(RequestPtr req, ThreadContext *tc,
315 Translation *translation, Mode mode,
316 ArmTranslationType tranType = NormalTran);
317 Fault translateComplete(RequestPtr req, ThreadContext *tc,
318 Translation *translation, Mode mode, ArmTranslationType tranType,
319 bool callFromS2);
320 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
321
322 void drainResume() override;
323
324 // Checkpointing
325 void serialize(CheckpointOut &cp) const override;
326 void unserialize(CheckpointIn &cp) override;
327
328 void regStats() override;
329
330 void regProbePoints() override;
331
332 /**
333 * Get the table walker master port. This is used for migrating
334 * port connections during a CPU takeOverFrom() call. For
335 * architectures that do not have a table walker, NULL is
336 * returned, hence the use of a pointer rather than a
337 * reference. For ARM this method will always return a valid port
338 * pointer.
339 *
340 * @return A pointer to the walker master port
341 */
342 BaseMasterPort* getMasterPort() override;
343
344 // Caching misc register values here.
345 // Writing to misc registers needs to invalidate them.
346 // translateFunctional/translateSe/translateFs checks if they are
347 // invalid and call updateMiscReg if necessary.
348protected:
349 CPSR cpsr;
350 bool aarch64;
351 ExceptionLevel aarch64EL;
352 SCTLR sctlr;
353 SCR scr;
354 bool isPriv;
355 bool isSecure;
356 bool isHyp;
357 TTBCR ttbcr;
358 uint16_t asid;
359 uint8_t vmid;
360 PRRR prrr;
361 NMRR nmrr;
362 HCR hcr;
363 uint32_t dacr;
364 bool miscRegValid;
365 ContextID miscRegContext;
366 ArmTranslationType curTranType;
367
368 // Cached copies of system-level properties
369 bool haveLPAE;
370 bool haveVirtualization;
371 bool haveLargeAsid64;
372
373 void updateMiscReg(ThreadContext *tc,
374 ArmTranslationType tranType = NormalTran);
375
376public:
377 const Params *
378 params() const
379 {
380 return dynamic_cast<const Params *>(_params);
381 }
382 inline void invalidateMiscReg() { miscRegValid = false; }
383
384private:
385 /** Remove any entries that match both a va and asn
386 * @param mva virtual address to flush
387 * @param asn contextid/asn to flush on match
388 * @param secure_lookup if the operation affects the secure world
389 * @param hyp if the operation affects hyp mode
390 * @param ignore_asn if the flush should ignore the asn
391 */
392 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
393 bool hyp, bool ignore_asn, uint8_t target_el);
394
395 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
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| 396
397 public: /* Testing */
398 Fault testTranslation(RequestPtr req, Mode mode,
399 TlbEntry::DomainType domain);
400 Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
401 TlbEntry::DomainType domain,
402 LookupLevel lookup_level);
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359};
360
361} // namespace ArmISA
362
363#endif // __ARCH_ARM_TLB_HH__
| 403};
404
405} // namespace ArmISA
406
407#endif // __ARCH_ARM_TLB_HH__
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