1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_TLB_HH__ 44#define __ARCH_ARM_TLB_HH__ 45 46 47#include "arch/arm/isa_traits.hh" 48#include "arch/arm/pagetable.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/vtophys.hh" 51#include "base/statistics.hh" 52#include "dev/dma_device.hh" 53#include "mem/request.hh" 54#include "params/ArmTLB.hh" 55#include "sim/fault_fwd.hh"
| 1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_TLB_HH__ 44#define __ARCH_ARM_TLB_HH__ 45 46 47#include "arch/arm/isa_traits.hh" 48#include "arch/arm/pagetable.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/vtophys.hh" 51#include "base/statistics.hh" 52#include "dev/dma_device.hh" 53#include "mem/request.hh" 54#include "params/ArmTLB.hh" 55#include "sim/fault_fwd.hh"
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134 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 135 136 bool bootUncacheability; 137 138 public: 139 TLB(const ArmTLBParams *p); 140 TLB(const Params *p, int _size, TableWalker *_walker); 141 142 /** Lookup an entry in the TLB 143 * @param vpn virtual address 144 * @param asn context id/address space id to use 145 * @param vmid The virtual machine ID used for stage 2 translation 146 * @param secure if the lookup is secure 147 * @param hyp if the lookup is done from hyp mode 148 * @param functional if the lookup should modify state 149 * @param ignore_asn if on lookup asn should be ignored 150 * @return pointer to TLB entry if it exists 151 */ 152 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 153 bool secure, bool functional, 154 bool ignore_asn, uint8_t target_el); 155 156 virtual ~TLB(); 157 158 void takeOverFrom(BaseTLB *otlb); 159 160 /// setup all the back pointers 161 virtual void init(); 162 163 void setMMU(Stage2MMU *m); 164 165 int getsize() const { return size; } 166 167 void insert(Addr vaddr, TlbEntry &pte); 168 169 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 170 Translation *translation, bool timing, bool functional, 171 bool is_secure, ArmTranslationType tranType); 172 173 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 174 Mode mode, Translation *translation, bool timing, 175 bool functional, TlbEntry *mergeTe); 176 177 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 178 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 179 ThreadContext *tc); 180 181 182 /** Reset the entire TLB 183 * @param secure_lookup if the operation affects the secure world 184 */ 185 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 186 bool ignore_el = false); 187 188 /** Remove all entries in the non secure world, depending on whether they 189 * were allocated in hyp mode or not 190 * @param hyp if the opperation affects hyp mode 191 */ 192 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 193 194 195 /** Reset the entire TLB. Used for CPU switching to prevent stale 196 * translations after multiple switches 197 */ 198 void flushAll() 199 { 200 flushAllSecurity(false, 0, true); 201 flushAllSecurity(true, 0, true); 202 } 203 204 /** Remove any entries that match both a va and asn 205 * @param mva virtual address to flush 206 * @param asn contextid/asn to flush on match 207 * @param secure_lookup if the operation affects the secure world 208 */ 209 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 210 uint8_t target_el); 211 212 /** Remove any entries that match the asn 213 * @param asn contextid/asn to flush on match 214 * @param secure_lookup if the operation affects the secure world 215 */ 216 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 217 218 /** Remove all entries that match the va regardless of asn 219 * @param mva address to flush from cache 220 * @param secure_lookup if the operation affects the secure world 221 * @param hyp if the operation affects hyp mode 222 */ 223 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 224 225 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 226 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 227 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); 228 229 void printTlb() const; 230 231 void allCpusCaching() { bootUncacheability = true; } 232 void demapPage(Addr vaddr, uint64_t asn) 233 { 234 // needed for x86 only 235 panic("demapPage() is not implemented.\n"); 236 } 237 238 static bool validVirtualAddress(Addr vaddr); 239 240 /** 241 * Do a functional lookup on the TLB (for debugging) 242 * and don't modify any internal state 243 * @param tc thread context to get the context id from 244 * @param vaddr virtual address to translate 245 * @param pa returned physical address 246 * @return if the translation was successful 247 */ 248 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 249 250 /** 251 * Do a functional lookup on the TLB (for checker cpu) that 252 * behaves like a normal lookup without modifying any page table state. 253 */ 254 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 255 ArmTranslationType tranType = NormalTran); 256 257 /** Accessor functions for memory attributes for last accessed TLB entry 258 */ 259 void 260 setAttr(uint64_t attr) 261 { 262 _attr = attr; 263 } 264 265 uint64_t 266 getAttr() const 267 { 268 return _attr; 269 } 270 271 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 272 Translation *translation, bool &delay, 273 bool timing, ArmTranslationType tranType, bool functional = false); 274 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 275 Translation *translation, bool &delay, bool timing); 276 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 277 ArmTranslationType tranType = NormalTran); 278 Fault translateTiming(RequestPtr req, ThreadContext *tc, 279 Translation *translation, Mode mode, 280 ArmTranslationType tranType = NormalTran); 281 Fault translateComplete(RequestPtr req, ThreadContext *tc, 282 Translation *translation, Mode mode, ArmTranslationType tranType, 283 bool callFromS2); 284 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 285 286 void drainResume(); 287 288 // Checkpointing 289 void serialize(std::ostream &os); 290 void unserialize(Checkpoint *cp, const std::string §ion); 291 292 void regStats(); 293
| 138 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 139 140 bool bootUncacheability; 141 142 public: 143 TLB(const ArmTLBParams *p); 144 TLB(const Params *p, int _size, TableWalker *_walker); 145 146 /** Lookup an entry in the TLB 147 * @param vpn virtual address 148 * @param asn context id/address space id to use 149 * @param vmid The virtual machine ID used for stage 2 translation 150 * @param secure if the lookup is secure 151 * @param hyp if the lookup is done from hyp mode 152 * @param functional if the lookup should modify state 153 * @param ignore_asn if on lookup asn should be ignored 154 * @return pointer to TLB entry if it exists 155 */ 156 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 157 bool secure, bool functional, 158 bool ignore_asn, uint8_t target_el); 159 160 virtual ~TLB(); 161 162 void takeOverFrom(BaseTLB *otlb); 163 164 /// setup all the back pointers 165 virtual void init(); 166 167 void setMMU(Stage2MMU *m); 168 169 int getsize() const { return size; } 170 171 void insert(Addr vaddr, TlbEntry &pte); 172 173 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 174 Translation *translation, bool timing, bool functional, 175 bool is_secure, ArmTranslationType tranType); 176 177 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 178 Mode mode, Translation *translation, bool timing, 179 bool functional, TlbEntry *mergeTe); 180 181 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 182 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 183 ThreadContext *tc); 184 185 186 /** Reset the entire TLB 187 * @param secure_lookup if the operation affects the secure world 188 */ 189 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 190 bool ignore_el = false); 191 192 /** Remove all entries in the non secure world, depending on whether they 193 * were allocated in hyp mode or not 194 * @param hyp if the opperation affects hyp mode 195 */ 196 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 197 198 199 /** Reset the entire TLB. Used for CPU switching to prevent stale 200 * translations after multiple switches 201 */ 202 void flushAll() 203 { 204 flushAllSecurity(false, 0, true); 205 flushAllSecurity(true, 0, true); 206 } 207 208 /** Remove any entries that match both a va and asn 209 * @param mva virtual address to flush 210 * @param asn contextid/asn to flush on match 211 * @param secure_lookup if the operation affects the secure world 212 */ 213 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 214 uint8_t target_el); 215 216 /** Remove any entries that match the asn 217 * @param asn contextid/asn to flush on match 218 * @param secure_lookup if the operation affects the secure world 219 */ 220 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 221 222 /** Remove all entries that match the va regardless of asn 223 * @param mva address to flush from cache 224 * @param secure_lookup if the operation affects the secure world 225 * @param hyp if the operation affects hyp mode 226 */ 227 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 228 229 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 230 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 231 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); 232 233 void printTlb() const; 234 235 void allCpusCaching() { bootUncacheability = true; } 236 void demapPage(Addr vaddr, uint64_t asn) 237 { 238 // needed for x86 only 239 panic("demapPage() is not implemented.\n"); 240 } 241 242 static bool validVirtualAddress(Addr vaddr); 243 244 /** 245 * Do a functional lookup on the TLB (for debugging) 246 * and don't modify any internal state 247 * @param tc thread context to get the context id from 248 * @param vaddr virtual address to translate 249 * @param pa returned physical address 250 * @return if the translation was successful 251 */ 252 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 253 254 /** 255 * Do a functional lookup on the TLB (for checker cpu) that 256 * behaves like a normal lookup without modifying any page table state. 257 */ 258 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 259 ArmTranslationType tranType = NormalTran); 260 261 /** Accessor functions for memory attributes for last accessed TLB entry 262 */ 263 void 264 setAttr(uint64_t attr) 265 { 266 _attr = attr; 267 } 268 269 uint64_t 270 getAttr() const 271 { 272 return _attr; 273 } 274 275 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 276 Translation *translation, bool &delay, 277 bool timing, ArmTranslationType tranType, bool functional = false); 278 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 279 Translation *translation, bool &delay, bool timing); 280 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 281 ArmTranslationType tranType = NormalTran); 282 Fault translateTiming(RequestPtr req, ThreadContext *tc, 283 Translation *translation, Mode mode, 284 ArmTranslationType tranType = NormalTran); 285 Fault translateComplete(RequestPtr req, ThreadContext *tc, 286 Translation *translation, Mode mode, ArmTranslationType tranType, 287 bool callFromS2); 288 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 289 290 void drainResume(); 291 292 // Checkpointing 293 void serialize(std::ostream &os); 294 void unserialize(Checkpoint *cp, const std::string §ion); 295 296 void regStats(); 297
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