tlb.hh (8229:78bf55f23338) | tlb.hh (8299:64a938a8b7fc) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 222 unchanged lines hidden (view full) --- 231 isPriv = cpsr.mode != MODE_USER; 232 contextId = tc->readMiscReg(MISCREG_CONTEXTIDR); 233 prrr = tc->readMiscReg(MISCREG_PRRR); 234 nmrr = tc->readMiscReg(MISCREG_NMRR); 235 dacr = tc->readMiscReg(MISCREG_DACR); 236 miscRegValid = true; 237 } 238public: | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 222 unchanged lines hidden (view full) --- 231 isPriv = cpsr.mode != MODE_USER; 232 contextId = tc->readMiscReg(MISCREG_CONTEXTIDR); 233 prrr = tc->readMiscReg(MISCREG_PRRR); 234 nmrr = tc->readMiscReg(MISCREG_NMRR); 235 dacr = tc->readMiscReg(MISCREG_DACR); 236 miscRegValid = true; 237 } 238public: |
239 const Params * 240 params() const 241 { 242 return dynamic_cast<const Params *>(_params); 243 } |
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239 inline void invalidateMiscReg() { miscRegValid = false; } 240}; 241 242} // namespace ArmISA 243 244#endif // __ARCH_ARM_TLB_HH__ | 244 inline void invalidateMiscReg() { miscRegValid = false; } 245}; 246 247} // namespace ArmISA 248 249#endif // __ARCH_ARM_TLB_HH__ |