tlb.hh (6020:0647c8b31a99) | tlb.hh (6116:a5a97b04d796) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * Copyright (c) 2007-2008 The Florida State University 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are --- 29 unchanged lines hidden (view full) --- 38#include <map> 39 40#include "arch/arm/isa_traits.hh" 41#include "arch/arm/utility.hh" 42#include "arch/arm/vtophys.hh" 43#include "arch/arm/pagetable.hh" 44#include "base/statistics.hh" 45#include "mem/request.hh" | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * Copyright (c) 2007-2008 The Florida State University 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are --- 29 unchanged lines hidden (view full) --- 38#include <map> 39 40#include "arch/arm/isa_traits.hh" 41#include "arch/arm/utility.hh" 42#include "arch/arm/vtophys.hh" 43#include "arch/arm/pagetable.hh" 44#include "base/statistics.hh" 45#include "mem/request.hh" |
46#include "params/ArmDTB.hh" 47#include "params/ArmITB.hh" | 46#include "params/ArmTLB.hh" |
48#include "sim/faults.hh" 49#include "sim/tlb.hh" 50 51class ThreadContext; 52 53/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB 54 However, to maintain compatibility with other architectures, we'll 55 simply create an ITLB and DTLB that will point to the real TLB */ --- 74 unchanged lines hidden (view full) --- 130 panic("demapPage unimplemented.\n"); 131 } 132 133 // static helper functions... really 134 static bool validVirtualAddress(Addr vaddr); 135 136 static Fault checkCacheability(RequestPtr &req); 137 | 47#include "sim/faults.hh" 48#include "sim/tlb.hh" 49 50class ThreadContext; 51 52/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB 53 However, to maintain compatibility with other architectures, we'll 54 simply create an ITLB and DTLB that will point to the real TLB */ --- 74 unchanged lines hidden (view full) --- 129 panic("demapPage unimplemented.\n"); 130 } 131 132 // static helper functions... really 133 static bool validVirtualAddress(Addr vaddr); 134 135 static Fault checkCacheability(RequestPtr &req); 136 |
137 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 138 void translateTiming(RequestPtr req, ThreadContext *tc, 139 Translation *translation, Mode mode); 140 |
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138 // Checkpointing 139 void serialize(std::ostream &os); 140 void unserialize(Checkpoint *cp, const std::string §ion); 141 142 void regStats(); 143}; 144 | 141 // Checkpointing 142 void serialize(std::ostream &os); 143 void unserialize(Checkpoint *cp, const std::string §ion); 144 145 void regStats(); 146}; 147 |
145class ITB : public TLB 146{ 147 public: 148 typedef ArmTLBParams Params; 149 ITB(const Params *p); | 148/* namespace ArmISA */ } |
150 | 149 |
151 Fault translateAtomic(RequestPtr req, ThreadContext *tc); 152 void translateTiming(RequestPtr req, ThreadContext *tc, 153 Translation *translation); 154}; 155 156class DTB : public TLB 157{ 158 public: 159 typedef ArmTLBParams Params; 160 DTB(const Params *p); 161 162 Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write); 163 void translateTiming(RequestPtr req, ThreadContext *tc, 164 Translation *translation, bool write); 165}; 166 167class UTB : public ITB, public DTB 168{ 169 public: 170 typedef ArmTLBParams Params; 171 UTB(const Params *p); 172 173}; 174 175} 176 | |
177#endif // __ARCH_ARM_TLB_HH__ | 150#endif // __ARCH_ARM_TLB_HH__ |