1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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54#include "params/ArmTLB.hh"
55#include "sim/faults.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TLB : public BaseTLB
63{
64 public:
65 enum ArmFlags {
66 AlignmentMask = 0x7,
67
68 AlignByte = 0x0,
69 AlignHalfWord = 0x1,
70 AlignWord = 0x3,
71 AlignDoubleWord = 0x7,
72
73 AllowUnaligned = 0x8,
74 // Because zero otherwise looks like a valid setting and may be used
75 // accidentally, this bit must be non-zero to show it was used on
76 // purpose.
77 MustBeOne = 0x10
78 };
79 protected:
80 typedef std::multimap<Addr, int> PageTable;
81 PageTable lookupTable; // Quick lookup into page table
82
83 ArmISA::PTE *table; // the Page Table
84 int size; // TLB Size
85 int nlu; // not last used entry (for replacement)
86
87 void nextnlu() { if (++nlu >= size) nlu = 0; }
88 ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
89
90 // Access Stats
91 mutable Stats::Scalar read_hits;
92 mutable Stats::Scalar read_misses;
93 mutable Stats::Scalar read_acv;
94 mutable Stats::Scalar read_accesses;
95 mutable Stats::Scalar write_hits;
96 mutable Stats::Scalar write_misses;
97 mutable Stats::Scalar write_acv;
98 mutable Stats::Scalar write_accesses;
99 Stats::Formula hits;
100 Stats::Formula misses;
101 Stats::Formula invalids;
102 Stats::Formula accesses;
103
104 public:
105 typedef ArmTLBParams Params;
106 TLB(const Params *p);
107
108 virtual ~TLB();
109 int getsize() const { return size; }
110
111 void insert(Addr vaddr, ArmISA::PTE &pte);
112 void flushAll();
113 void demapPage(Addr vaddr, uint64_t asn)
114 {
115 panic("demapPage unimplemented.\n");
116 }
117
118 static bool validVirtualAddress(Addr vaddr);
119
120 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
121 void translateTiming(RequestPtr req, ThreadContext *tc,
122 Translation *translation, Mode mode);
123
124 // Checkpointing
125 void serialize(std::ostream &os);
126 void unserialize(Checkpoint *cp, const std::string &section);
127
128 void regStats();
129};
130
131/* namespace ArmISA */ }
132
133#endif // __ARCH_ARM_TLB_HH__