1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 29 unchanged lines hidden (view full) ---

38#include <map>
39
40#include "arch/arm/isa_traits.hh"
41#include "arch/arm/utility.hh"
42#include "arch/arm/vtophys.hh"
43#include "arch/arm/pagetable.hh"
44#include "base/statistics.hh"
45#include "mem/request.hh"
46#include "params/ArmTLB.hh"
47#include "sim/faults.hh"
48#include "sim/tlb.hh"
49
50class ThreadContext;
51
52/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB
53 However, to maintain compatibility with other architectures, we'll
54 simply create an ITLB and DTLB that will point to the real TLB */

--- 74 unchanged lines hidden (view full) ---

129 panic("demapPage unimplemented.\n");
130 }
131
132 // static helper functions... really
133 static bool validVirtualAddress(Addr vaddr);
134
135 static Fault checkCacheability(RequestPtr &req);
136
137 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
138 void translateTiming(RequestPtr req, ThreadContext *tc,
139 Translation *translation, Mode mode);
140
141 // Checkpointing
142 void serialize(std::ostream &os);
143 void unserialize(Checkpoint *cp, const std::string &section);
144
145 void regStats();
146};
147
148/* namespace ArmISA */ }
149
150#endif // __ARCH_ARM_TLB_HH__