tlb.cc (9950:4b7f60080149) tlb.cc (10024:fc10e1f9f124)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include "arch/arm/pagetable.hh"
50#include "arch/arm/system.hh"
51#include "arch/arm/table_walker.hh"
52#include "arch/arm/tlb.hh"
53#include "arch/arm/utility.hh"
54#include "base/inifile.hh"
55#include "base/str.hh"
56#include "base/trace.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include "arch/arm/pagetable.hh"
50#include "arch/arm/system.hh"
51#include "arch/arm/table_walker.hh"
52#include "arch/arm/tlb.hh"
53#include "arch/arm/utility.hh"
54#include "base/inifile.hh"
55#include "base/str.hh"
56#include "base/trace.hh"
57#include "cpu/base.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Checkpoint.hh"
59#include "debug/TLB.hh"
60#include "debug/TLBVerbose.hh"
61#include "mem/page_table.hh"
62#include "params/ArmTLB.hh"
63#include "sim/full_system.hh"
64#include "sim/process.hh"

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472 bool is_fetch = (mode == Execute);
473 bool is_write = (mode == Write);
474 bool is_priv = isPriv && !(flags & UserMode);
475
476 req->setAsid(contextId.asid);
477 if (is_priv)
478 req->setFlags(Request::PRIVILEGED);
479
58#include "cpu/thread_context.hh"
59#include "debug/Checkpoint.hh"
60#include "debug/TLB.hh"
61#include "debug/TLBVerbose.hh"
62#include "mem/page_table.hh"
63#include "params/ArmTLB.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"

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473 bool is_fetch = (mode == Execute);
474 bool is_write = (mode == Write);
475 bool is_priv = isPriv && !(flags & UserMode);
476
477 req->setAsid(contextId.asid);
478 if (is_priv)
479 req->setFlags(Request::PRIVILEGED);
480
481 req->taskId(tc->getCpuPtr()->taskId());
482
480 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
481 isPriv, flags & UserMode);
482 // If this is a clrex instruction, provide a PA of 0 with no fault
483 // This will force the monitor to set the tracked address to 0
484 // a bit of a hack but this effectively clrears this processors monitor
485 if (flags & Request::CLEAR_LL){
486 req->setPaddr(0);
487 req->setFlags(Request::UNCACHEABLE);

--- 265 unchanged lines hidden --- 		483 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
484 isPriv, flags & UserMode);
485 // If this is a clrex instruction, provide a PA of 0 with no fault
486 // This will force the monitor to set the tracked address to 0
487 // a bit of a hack but this effectively clrears this processors monitor
488 if (flags & Request::CLEAR_LL){
489 req->setPaddr(0);
490 req->setFlags(Request::UNCACHEABLE);

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