tlb.cc (8782:10c9297e14d5) tlb.cc (8806:669e93d79ed9)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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413 assert(flags & MustBeOne);
414 if (sctlr.a || !(flags & AllowUnaligned)) {
415 if (vaddr & flags & AlignmentMask) {
416 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
417 }
418 }
419 }
420
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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413 assert(flags & MustBeOne);
414 if (sctlr.a || !(flags & AllowUnaligned)) {
415 if (vaddr & flags & AlignmentMask) {
416 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
417 }
418 }
419 }
420
421 if (!FullSystem) {
422 Addr paddr;
423 Process *p = tc->getProcessPtr();
421 Addr paddr;
422 Process *p = tc->getProcessPtr();
424
423
425 if (!p->pTable->translate(vaddr, paddr))
426 return Fault(new GenericPageTableFault(vaddr));
427 req->setPaddr(paddr);
428 }
424 if (!p->pTable->translate(vaddr, paddr))
425 return Fault(new GenericPageTableFault(vaddr));
426 req->setPaddr(paddr);
429
430 return NoFault;
431}
432
433Fault
434TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
435{
436 return NoFault;

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565 req->setFlags(Request::UNCACHEABLE);
566
567 // Prevent prefetching from I/O devices.
568 if (req->isPrefetch()) {
569 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
570 }
571 }
572
427
428 return NoFault;
429}
430
431Fault
432TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
433{
434 return NoFault;

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563 req->setFlags(Request::UNCACHEABLE);
564
565 // Prevent prefetching from I/O devices.
566 if (req->isPrefetch()) {
567 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
568 }
569 }
570
573 if (FullSystem) {
574 if (!bootUncacheability &&
575 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
576 req->setFlags(Request::UNCACHEABLE);
577 }
571 if (!bootUncacheability &&
572 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
573 req->setFlags(Request::UNCACHEABLE);
578
579 switch ( (dacr >> (te->domain * 2)) & 0x3) {
580 case 0:
581 domainFaults++;
582 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
583 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
584 if (is_fetch)
585 return new PrefetchAbort(vaddr,

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575 switch ( (dacr >> (te->domain * 2)) & 0x3) {
576 case 0:
577 domainFaults++;
578 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
579 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
580 if (is_fetch)
581 return new PrefetchAbort(vaddr,

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