tlb.cc (8552:f51e3dce9521) tlb.cc (8733:64a7bf8fa56c)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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448TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
449 bool is_write, uint8_t domain, bool sNp)
450{
451 return NoFault;
452}
453
454Fault
455TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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448TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
449 bool is_write, uint8_t domain, bool sNp)
450{
451 return NoFault;
452}
453
454Fault
455TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
456 Translation *translation, bool &delay, bool timing)
456 Translation *translation, bool &delay, bool timing, bool functional)
457{
457{
458 // No such thing as a functional timing access
459 assert(!(timing && functional));
460
458 if (!miscRegValid) {
459 updateMiscReg(tc);
460 DPRINTF(TLBVerbose, "TLB variables changed!\n");
461 }
462
463 Addr vaddr = req->getVaddr();
464 uint32_t flags = req->getFlags();
465

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536 else
537 readMisses++;
538
539 // start translation table walk, pass variables rather than
540 // re-retreaving in table walker for speed
541 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
542 vaddr, contextId);
543 fault = tableWalker->walk(req, tc, contextId, mode, translation,
461 if (!miscRegValid) {
462 updateMiscReg(tc);
463 DPRINTF(TLBVerbose, "TLB variables changed!\n");
464 }
465
466 Addr vaddr = req->getVaddr();
467 uint32_t flags = req->getFlags();
468

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539 else
540 readMisses++;
541
542 // start translation table walk, pass variables rather than
543 // re-retreaving in table walker for speed
544 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
545 vaddr, contextId);
546 fault = tableWalker->walk(req, tc, contextId, mode, translation,
544 timing);
547 timing, functional);
545 if (timing && fault == NoFault) {
546 delay = true;
547 // for timing mode, return and wait for table walk
548 return fault;
549 }
550 if (fault)
551 return fault;
552

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696#else
697 fault = translateSe(req, tc, mode, NULL, delay, false);
698#endif
699 assert(!delay);
700 return fault;
701}
702
703Fault
548 if (timing && fault == NoFault) {
549 delay = true;
550 // for timing mode, return and wait for table walk
551 return fault;
552 }
553 if (fault)
554 return fault;
555

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699#else
700 fault = translateSe(req, tc, mode, NULL, delay, false);
701#endif
702 assert(!delay);
703 return fault;
704}
705
706Fault
707TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
708{
709 bool delay = false;
710 Fault fault;
711#if FULL_SYSTEM
712 fault = translateFs(req, tc, mode, NULL, delay, false, true);
713#else
714 fault = translateSe(req, tc, mode, NULL, delay, false);
715#endif
716 assert(!delay);
717 return fault;
718}
719
720Fault
704TLB::translateTiming(RequestPtr req, ThreadContext *tc,
705 Translation *translation, Mode mode)
706{
707 assert(translation);
708 bool delay = false;
709 Fault fault;
710#if FULL_SYSTEM
711 fault = translateFs(req, tc, mode, translation, delay, true);

--- 29 unchanged lines hidden --- 		721TLB::translateTiming(RequestPtr req, ThreadContext *tc,
722 Translation *translation, Mode mode)
723{
724 assert(translation);
725 bool delay = false;
726 Fault fault;
727#if FULL_SYSTEM
728 fault = translateFs(req, tc, mode, translation, delay, true);

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