tlb.cc (8353:237ea6324ece) | tlb.cc (8527:6bac5b04d588) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 47 unchanged lines hidden (view full) --- 56#include "debug/Checkpoint.hh" 57#include "debug/TLB.hh" 58#include "debug/TLBVerbose.hh" 59#include "mem/page_table.hh" 60#include "params/ArmTLB.hh" 61#include "sim/process.hh" 62 63#if FULL_SYSTEM | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 47 unchanged lines hidden (view full) --- 56#include "debug/Checkpoint.hh" 57#include "debug/TLB.hh" 58#include "debug/TLBVerbose.hh" 59#include "mem/page_table.hh" 60#include "params/ArmTLB.hh" 61#include "sim/process.hh" 62 63#if FULL_SYSTEM |
64#include "arch/arm/system.hh" |
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64#include "arch/arm/table_walker.hh" 65#endif 66 67using namespace std; 68using namespace ArmISA; 69 70TLB::TLB(const Params *p) 71 : BaseTLB(p), size(p->size) 72#if FULL_SYSTEM 73 , tableWalker(p->walker) 74#endif | 65#include "arch/arm/table_walker.hh" 66#endif 67 68using namespace std; 69using namespace ArmISA; 70 71TLB::TLB(const Params *p) 72 : BaseTLB(p), size(p->size) 73#if FULL_SYSTEM 74 , tableWalker(p->walker) 75#endif |
75 , rangeMRU(1), miscRegValid(false) | 76 , rangeMRU(1), bootUncacheability(false), miscRegValid(false) |
76{ 77 table = new TlbEntry[size]; 78 memset(table, 0, sizeof(TlbEntry) * size); 79 80#if FULL_SYSTEM 81 tableWalker->setTlb(this); 82#endif 83} --- 486 unchanged lines hidden (view full) --- 570 req->setFlags(Request::UNCACHEABLE); 571 572 // Prevent prefetching from I/O devices. 573 if (req->isPrefetch()) { 574 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 575 } 576 } 577 | 77{ 78 table = new TlbEntry[size]; 79 memset(table, 0, sizeof(TlbEntry) * size); 80 81#if FULL_SYSTEM 82 tableWalker->setTlb(this); 83#endif 84} --- 486 unchanged lines hidden (view full) --- 571 req->setFlags(Request::UNCACHEABLE); 572 573 // Prevent prefetching from I/O devices. 574 if (req->isPrefetch()) { 575 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 576 } 577 } 578 |
579 580 if (!bootUncacheability && 581 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) 582 req->setFlags(Request::UNCACHEABLE); 583 |
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578 switch ( (dacr >> (te->domain * 2)) & 0x3) { 579 case 0: 580 domainFaults++; 581 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 582 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 583 if (is_fetch) 584 return new PrefetchAbort(vaddr, 585 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); --- 113 unchanged lines hidden (view full) --- 699 assert(translation); 700 bool delay = false; 701 Fault fault; 702#if FULL_SYSTEM 703 fault = translateFs(req, tc, mode, translation, delay, true); 704#else 705 fault = translateSe(req, tc, mode, translation, delay, true); 706#endif | 584 switch ( (dacr >> (te->domain * 2)) & 0x3) { 585 case 0: 586 domainFaults++; 587 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 588 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 589 if (is_fetch) 590 return new PrefetchAbort(vaddr, 591 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); --- 113 unchanged lines hidden (view full) --- 705 assert(translation); 706 bool delay = false; 707 Fault fault; 708#if FULL_SYSTEM 709 fault = translateFs(req, tc, mode, translation, delay, true); 710#else 711 fault = translateSe(req, tc, mode, translation, delay, true); 712#endif |
707 DPRINTF(TLB, "Translation returning delay=%d fault=%d\n", delay, fault != | 713 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != |
708 NoFault); 709 if (!delay) 710 translation->finish(fault, req, tc, mode); 711 else 712 translation->markDelayed(); 713 return fault; 714} 715 --- 17 unchanged lines hidden --- | 714 NoFault); 715 if (!delay) 716 translation->finish(fault, req, tc, mode); 717 else 718 translation->markDelayed(); 719 return fault; 720} 721 --- 17 unchanged lines hidden --- |