tlb.cc (7705:fd65f85fcc0c) tlb.cc (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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311}
312
313#if !FULL_SYSTEM
314Fault
315TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
316 Translation *translation, bool &delay, bool timing)
317{
318 // XXX Cache misc registers and have miscreg write function inv cache
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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311}
312
313#if !FULL_SYSTEM
314Fault
315TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
316 Translation *translation, bool &delay, bool timing)
317{
318 // XXX Cache misc registers and have miscreg write function inv cache
319 Addr vaddr = req->getVaddr() & ~PcModeMask;
319 Addr vaddr = req->getVaddr();
320 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
321 uint32_t flags = req->getFlags();
322
323 bool is_fetch = (mode == Execute);
324 bool is_write = (mode == Write);
325
326 if (!is_fetch) {
327 assert(flags & MustBeOne);

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357 return NoFault;
358}
359
360Fault
361TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
362 Translation *translation, bool &delay, bool timing)
363{
364 // XXX Cache misc registers and have miscreg write function inv cache
320 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
321 uint32_t flags = req->getFlags();
322
323 bool is_fetch = (mode == Execute);
324 bool is_write = (mode == Write);
325
326 if (!is_fetch) {
327 assert(flags & MustBeOne);

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357 return NoFault;
358}
359
360Fault
361TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
362 Translation *translation, bool &delay, bool timing)
363{
364 // XXX Cache misc registers and have miscreg write function inv cache
365 Addr vaddr = req->getVaddr() & ~PcModeMask;
365 Addr vaddr = req->getVaddr();
366 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
367 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
368 uint32_t flags = req->getFlags();
369
370 bool is_fetch = (mode == Execute);
371 bool is_write = (mode == Write);
372 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
373

--- 227 unchanged lines hidden --- 		366 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
367 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
368 uint32_t flags = req->getFlags();
369
370 bool is_fetch = (mode == Execute);
371 bool is_write = (mode == Write);
372 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
373

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