tlb.cc (7399:a378ac1e1615) tlb.cc (7404:bfc74724914e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 33 unchanged lines hidden (view full) ---

42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 33 unchanged lines hidden (view full) ---

42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/table_walker.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "mem/page_table.hh"
57#include "params/ArmTLB.hh"
58#include "sim/process.hh"
59
51#include "arch/arm/tlb.hh"
52#include "arch/arm/utility.hh"
53#include "base/inifile.hh"
54#include "base/str.hh"
55#include "base/trace.hh"
56#include "cpu/thread_context.hh"
57#include "mem/page_table.hh"
58#include "params/ArmTLB.hh"
59#include "sim/process.hh"
60
60
61using namespace std;
62using namespace ArmISA;
63
64TLB::TLB(const Params *p)
65 : BaseTLB(p), size(p->size), nlu(0)
61using namespace std;
62using namespace ArmISA;
63
64TLB::TLB(const Params *p)
65 : BaseTLB(p), size(p->size), nlu(0)
66#if FULL_SYSTEM
67 , tableWalker(p->walker)
68#endif
66{
69{
67 table = new ArmISA::PTE[size];
68 memset(table, 0, sizeof(ArmISA::PTE[size]));
70 table = new TlbEntry[size];
71 memset(table, 0, sizeof(TlbEntry[size]));
69
72
73 tableWalker->setTlb(this);
70}
71
72TLB::~TLB()
73{
74 if (table)
75 delete [] table;
76}
77
74}
75
76TLB::~TLB()
77{
78 if (table)
79 delete [] table;
80}
81
78ArmISA::PTE *
79TLB::lookup(Addr vpn, uint8_t asn) const
82TlbEntry*
83TLB::lookup(Addr va, uint8_t cid)
80{
84{
81 panic("lookup() not implemented for ARM\n");
85 // XXX This should either turn into a TlbMap or add caching
86
87 TlbEntry *retval = NULL;
88
89 // Do some kind of caching, fast indexing, anything
90
91 int x = 0;
92 while (retval == NULL && x < size) {
93 if (table[x].match(va, cid)) {
94 retval = &table[x];
95 if (x == nlu)
96 nextnlu();
97
98 break;
99 }
100 x++;
101 }
102
103 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
104 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
105 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
106 retval ? retval->ap : 0);
107 ;
108 return retval;
82}
83
84// insert a new TLB entry
85void
109}
110
111// insert a new TLB entry
112void
86TLB::insert(Addr addr, ArmISA::PTE &pte)
113TLB::insert(Addr addr, TlbEntry &entry)
87{
114{
88 fatal("TLB Insert not yet implemented\n");
115 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
116 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
117 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
118 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
119 entry.xn, entry.ap, entry.domain);
120
121 if (table[nlu].valid)
122 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
123 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N,
124 table[nlu].size, table[nlu].ap);
125
126 // XXX Update caching, lookup table etc
127 table[nlu] = entry;
128
129 // XXX Figure out how entries are generally inserted in ARM
130 nextnlu();
89}
90
91void
131}
132
133void
134TLB::printTlb()
135{
136 int x = 0;
137 TlbEntry *te;
138 DPRINTF(TLB, "Current TLB contents:\n");
139 while (x < size) {
140 te = &table[x];
141 if (te->valid)
142 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
143 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
144 x++;
145 }
146}
147
148
149void
92TLB::flushAll()
93{
150TLB::flushAll()
151{
94 DPRINTF(TLB, "flushAll\n");
95 memset(table, 0, sizeof(ArmISA::PTE[size]));
96 lookupTable.clear();
152 DPRINTF(TLB, "Flushing all TLB entries\n");
153 int x = 0;
154 TlbEntry *te;
155 while (x < size) {
156 te = &table[x];
157 if (te->valid)
158 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
159 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
160 x++;
161 }
162
163 memset(table, 0, sizeof(TlbEntry[size]));
97 nlu = 0;
98}
99
164 nlu = 0;
165}
166
167
100void
168void
101TLB::serialize(ostream &os)
169TLB::flushMvaAsid(Addr mva, uint64_t asn)
102{
170{
103 SERIALIZE_SCALAR(size);
104 SERIALIZE_SCALAR(nlu);
171 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
172 TlbEntry *te;
105
173
106 for (int i = 0; i < size; i++) {
107 nameOut(os, csprintf("%s.PTE%d", name(), i));
108 table[i].serialize(os);
174 te = lookup(mva, asn);
175 while (te != NULL) {
176 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
177 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
178 te->valid = false;
179 te = lookup(mva,asn);
109 }
110}
111
112void
180 }
181}
182
183void
184TLB::flushAsid(uint64_t asn)
185{
186 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
187
188 int x = 0;
189 TlbEntry *te;
190
191 while (x < size) {
192 te = &table[x];
193 if (te->asid == asn) {
194 te->valid = false;
195 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
196 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
197 }
198 x++;
199 }
200}
201
202void
203TLB::flushMva(Addr mva)
204{
205 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
206
207 int x = 0;
208 TlbEntry *te;
209
210 while (x < size) {
211 te = &table[x];
212 Addr v = te->vpn << te->N;
213 if (mva >= v && mva < v + te->size) {
214 te->valid = false;
215 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
216 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
217 }
218 x++;
219 }
220}
221
222void
223TLB::serialize(ostream &os)
224{
225 panic("Implement Serialize\n");
226}
227
228void
113TLB::unserialize(Checkpoint *cp, const string &section)
114{
229TLB::unserialize(Checkpoint *cp, const string &section)
230{
115 UNSERIALIZE_SCALAR(size);
116 UNSERIALIZE_SCALAR(nlu);
117
118 panic("Need to properly unserialize TLB\n");
231
232 panic("Need to properly unserialize TLB\n");
119 for (int i = 0; i < size; i++) {
120 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
121 }
122}
123
124void
125TLB::regStats()
126{
127 read_hits
128 .name(name() + ".read_hits")
129 .desc("DTB read hits")

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177 ;
178
179 hits = read_hits + write_hits;
180 misses = read_misses + write_misses;
181 accesses = read_accesses + write_accesses;
182}
183
184Fault
233}
234
235void
236TLB::regStats()
237{
238 read_hits
239 .name(name() + ".read_hits")
240 .desc("DTB read hits")

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288 ;
289
290 hits = read_hits + write_hits;
291 misses = read_misses + write_misses;
292 accesses = read_accesses + write_accesses;
293}
294
295Fault
185TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
296TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
186{
297{
298 return NoFault;
299}
300
301Fault
302TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
303 uint8_t domain, bool sNp)
304{
305 return NoFault;
306}
307
308#if !FULL_SYSTEM
309Fault
310TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
311 Translation *translation, bool &delay, bool timing)
312{
313 // XXX Cache misc registers and have miscreg write function inv cache
187 Addr vaddr = req->getVaddr() & ~PcModeMask;
188 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
189 uint32_t flags = req->getFlags();
190
314 Addr vaddr = req->getVaddr() & ~PcModeMask;
315 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
316 uint32_t flags = req->getFlags();
317
191 if (mode != Execute) {
192 assert(flags & MustBeOne);
318 bool is_fetch = (mode == Execute);
319 bool is_write = (mode == Write);
193
320
194 if (sctlr.a || (flags & AllowUnaligned) == 0) {
195 if ((vaddr & flags & AlignmentMask) != 0) {
196 return new DataAbort(vaddr, (mode == Write), 0,
197 ArmFault::AlignmentFault);
321 if (!is_fetch) {
322 assert(flags & MustBeOne);
323 if (sctlr.a || !(flags & AllowUnaligned)) {
324 if (vaddr & flags & AlignmentMask) {
325 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
198 }
199 }
200 }
326 }
327 }
328 }
201#if !FULL_SYSTEM
202 Process * p = tc->getProcessPtr();
203
204 Addr paddr;
329
330 Addr paddr;
331 Process *p = tc->getProcessPtr();
332
205 if (!p->pTable->translate(vaddr, paddr))
206 return Fault(new GenericPageTableFault(vaddr));
207 req->setPaddr(paddr);
208
209 return NoFault;
333 if (!p->pTable->translate(vaddr, paddr))
334 return Fault(new GenericPageTableFault(vaddr));
335 req->setPaddr(paddr);
336
337 return NoFault;
210#else
338}
339
340#else // FULL_SYSTEM
341
342Fault
343TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
344 Translation *translation, bool &delay, bool timing)
345{
346 // XXX Cache misc registers and have miscreg write function inv cache
347 Addr vaddr = req->getVaddr() & ~PcModeMask;
348 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
350 uint32_t flags = req->getFlags();
351
352 bool is_fetch = (mode == Execute);
353 bool is_write = (mode == Write);
354 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
355
356 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
357 & UserMode);
358 if (!is_fetch) {
359 assert(flags & MustBeOne);
360 if (sctlr.a || !(flags & AllowUnaligned)) {
361 if (vaddr & flags & AlignmentMask) {
362 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
363 }
364 }
365 }
366
367 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
368 Fault fault;
369
370
211 if (!sctlr.m) {
212 req->setPaddr(vaddr);
371 if (!sctlr.m) {
372 req->setPaddr(vaddr);
373 if (sctlr.tre == 0) {
374 req->setFlags(Request::UNCACHEABLE);
375 } else {
376 PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
377 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
378
379 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
380 req->setFlags(Request::UNCACHEABLE);
381 }
382 return trickBoxCheck(req, mode, 0, false);
383 }
384
385 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id);
386 // Translation enabled
387
388 TlbEntry *te = lookup(vaddr, context_id);
389 if (te == NULL) {
390 // start translation table walk, pass variables rather than
391 // re-retreaving in table walker for speed
392 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
393 vaddr, context_id);
394 fault = tableWalker->walk(req, tc, context_id, mode, translation,
395 timing);
396 if (timing)
397 delay = true;
398 if (fault)
399 return fault;
400
401 te = lookup(vaddr, context_id);
402 if (!te)
403 printTlb();
404 assert(te);
405 }
406
407 uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
408 switch ( (dacr >> (te->domain * 2)) & 0x3) {
409 case 0:
410 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
411 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
412 if (is_fetch)
413 return new PrefetchAbort(vaddr,
414 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
415 else
416 return new DataAbort(vaddr, te->domain, is_write,
417 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
418 case 1:
419 // Continue with permissions check
420 break;
421 case 2:
422 panic("UNPRED domain\n");
423 case 3:
424 req->setPaddr(te->pAddr(vaddr));
425 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
426 if (fault)
427 return fault;
213 return NoFault;
214 }
428 return NoFault;
429 }
215 warn_once("MPU translation not implemented\n");
216 req->setPaddr(vaddr);
430
431 uint8_t ap = te->ap;
432
433 if (sctlr.afe == 1)
434 ap |= 1;
435
436 bool abt;
437
438 switch (ap) {
439 case 0:
440 abt = true;
441 break;
442 case 1:
443 abt = !is_priv;
444 break;
445 case 2:
446 abt = !is_priv && is_write;
447 break;
448 case 3:
449 abt = false;
450 break;
451 case 4:
452 panic("UNPRED premissions\n");
453 case 5:
454 abt = !is_priv || is_write;
455 break;
456 case 6:
457 case 7:
458 abt = is_write;
459 break;
460 default:
461 panic("Unknown permissions\n");
462 }
463 if ((is_fetch) && (abt || te->xn)) {
464 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
465 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
466 return new PrefetchAbort(vaddr,
467 (te->sNp ? ArmFault::Permission0 :
468 ArmFault::Permission1));
469 } else if (abt) {
470 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
471 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
472 return new DataAbort(vaddr, te->domain, is_write,
473 (te->sNp ? ArmFault::Permission0 :
474 ArmFault::Permission1));
475 }
476
477 req->setPaddr(te->pAddr(vaddr));
478 // Check for a trickbox generated address fault
479 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
480 if (fault)
481 return fault;
482
217 return NoFault;
483 return NoFault;
218
484}
219
220#endif
485
486#endif
487
488Fault
489TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
490{
491 bool delay = false;
492 Fault fault;
493#if FULL_SYSTEM
494 fault = translateFs(req, tc, mode, NULL, delay, false);
495#else
496 fault = translateSe(req, tc, mode, NULL, delay, false);
497#endif
498 assert(!delay);
499 return fault;
221}
222
500}
501
223void
502Fault
224TLB::translateTiming(RequestPtr req, ThreadContext *tc,
225 Translation *translation, Mode mode)
226{
227 assert(translation);
503TLB::translateTiming(RequestPtr req, ThreadContext *tc,
504 Translation *translation, Mode mode)
505{
506 assert(translation);
228 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
507 bool delay = false;
508 Fault fault;
509#if FULL_SYSTEM
510 fault = translateFs(req, tc, mode, translation, delay, true);
511#else
512 fault = translateSe(req, tc, mode, translation, delay, true);
513#endif
514 if (!delay)
515 translation->finish(fault, req, tc, mode);
516 return fault;
229}
230
231ArmISA::TLB *
232ArmTLBParams::create()
233{
234 return new ArmISA::TLB(this);
235}
517}
518
519ArmISA::TLB *
520ArmTLBParams::create()
521{
522 return new ArmISA::TLB(this);
523}