tlb.cc (6020:0647c8b31a99) tlb.cc (6116:a5a97b04d796)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 22 unchanged lines hidden (view full) ---

31 * Steve Reinhardt
32 * Jaidev Patwardhan
33 * Stephen Hines
34 */
35
36#include <string>
37#include <vector>
38
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 22 unchanged lines hidden (view full) ---

31 * Steve Reinhardt
32 * Jaidev Patwardhan
33 * Stephen Hines
34 */
35
36#include <string>
37#include <vector>
38
39#include "arch/arm/faults.hh"
39#include "arch/arm/pagetable.hh"
40#include "arch/arm/tlb.hh"
40#include "arch/arm/pagetable.hh"
41#include "arch/arm/tlb.hh"
41#include "arch/arm/faults.hh"
42#include "arch/arm/utility.hh"
43#include "base/inifile.hh"
44#include "base/str.hh"
45#include "base/trace.hh"
46#include "cpu/thread_context.hh"
42#include "arch/arm/utility.hh"
43#include "base/inifile.hh"
44#include "base/str.hh"
45#include "base/trace.hh"
46#include "cpu/thread_context.hh"
47#include "sim/process.hh"
48#include "mem/page_table.hh"
47#include "mem/page_table.hh"
49#include "params/ArmDTB.hh"
50#include "params/ArmITB.hh"
51#include "params/ArmTLB.hh"
48#include "params/ArmTLB.hh"
52#include "params/ArmUTB.hh"
49#include "sim/process.hh"
53
54
55using namespace std;
56using namespace ArmISA;
57
58///////////////////////////////////////////////////////////////////////
59//
60// ARM TLB

--- 213 unchanged lines hidden (view full) ---

274 ;
275
276 hits = read_hits + write_hits;
277 misses = read_misses + write_misses;
278 accesses = read_accesses + write_accesses;
279}
280
281Fault
50
51
52using namespace std;
53using namespace ArmISA;
54
55///////////////////////////////////////////////////////////////////////
56//
57// ARM TLB

--- 213 unchanged lines hidden (view full) ---

271 ;
272
273 hits = read_hits + write_hits;
274 misses = read_misses + write_misses;
275 accesses = read_accesses + write_accesses;
276}
277
278Fault
282ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
279TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
283{
284#if !FULL_SYSTEM
285 Process * p = tc->getProcessPtr();
286
287 Fault fault = p->pTable->translate(req);
288 if(fault != NoFault)
289 return fault;
290
291 return NoFault;
292#else
280{
281#if !FULL_SYSTEM
282 Process * p = tc->getProcessPtr();
283
284 Fault fault = p->pTable->translate(req);
285 if(fault != NoFault)
286 return fault;
287
288 return NoFault;
289#else
293 fatal("ITB translate not yet implemented\n");
290 fatal("translate atomic not yet implemented\n");
294#endif
295}
296
297void
291#endif
292}
293
294void
298ITB::translateTiming(RequestPtr req, ThreadContext *tc,
299 Translation *translation)
295TLB::translateTiming(RequestPtr req, ThreadContext *tc,
296 Translation *translation, Mode mode)
300{
301 assert(translation);
297{
298 assert(translation);
302 translation->finish(translateAtomic(req, tc), req, tc, false);
299 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
303}
304
300}
301
305
306Fault
307DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
308{
309#if !FULL_SYSTEM
310 Process * p = tc->getProcessPtr();
311
312 Fault fault = p->pTable->translate(req);
313 if(fault != NoFault)
314 return fault;
315
316 return NoFault;
317#else
318 fatal("DTB translate not yet implemented\n");
319#endif
320}
321
322void
323DTB::translateTiming(RequestPtr req, ThreadContext *tc,
324 Translation *translation, bool write)
325{
326 assert(translation);
327 translation->finish(translateAtomic(req, tc, write), req, tc, write);
328}
329
330///////////////////////////////////////////////////////////////////////
331//
332// Arm ITB
333//
334ITB::ITB(const Params *p)
335 : TLB(p)
336{}
337
338
339///////////////////////////////////////////////////////////////////////
340//
341// Arm DTB
342//
343DTB::DTB(const Params *p)
344 : TLB(p)
345{}
346
347///////////////////////////////////////////////////////////////////////
348//
349// Arm UTB
350//
351UTB::UTB(const Params *p)
352 : ITB(p), DTB(p)
353{}
354
355ArmISA::PTE &
356TLB::index(bool advance)
357{
358 ArmISA::PTE *pte = &table[nlu];
359
360 if (advance)
361 nextnlu();
362
363 return *pte;
364}
365
302ArmISA::PTE &
303TLB::index(bool advance)
304{
305 ArmISA::PTE *pte = &table[nlu];
306
307 if (advance)
308 nextnlu();
309
310 return *pte;
311}
312
366ArmISA::ITB *
367ArmITBParams::create()
313ArmISA::TLB *
314ArmTLBParams::create()
368{
315{
369 return new ArmISA::ITB(this);
316 return new ArmISA::TLB(this);
370}
317}
371
372ArmISA::DTB *
373ArmDTBParams::create()
374{
375 return new ArmISA::DTB(this);
376}
377
378ArmISA::UTB *
379ArmUTBParams::create()
380{
381 return new ArmISA::UTB(this);
382}