tlb.cc (14088:8de55a7aa53b) tlb.cc (14128:6ed23d07d0d1)
1/*
2 * Copyright (c) 2010-2013, 2016-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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899 break;
900 default:
901 grant = false;
902 }
903 }
904 break;
905 case EL1:
906 {
1/*
2 * Copyright (c) 2010-2013, 2016-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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899 break;
900 default:
901 grant = false;
902 }
903 }
904 break;
905 case EL1:
906 {
907 if (checkPAN(tc, ap, req, mode)) {
908 grant = false;
909 break;
910 }
911
907 uint8_t perm = (ap << 2) | (xn << 1) | pxn;
908 switch (perm) {
909 case 0:
910 case 2:
911 grant = r || w || (x && !sctlr.wxn);
912 break;
913 case 1:
914 case 3:

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933 grant = r;
934 break;
935 default:
936 grant = false;
937 }
938 }
939 break;
940 case EL2:
912 uint8_t perm = (ap << 2) | (xn << 1) | pxn;
913 switch (perm) {
914 case 0:
915 case 2:
916 grant = r || w || (x && !sctlr.wxn);
917 break;
918 case 1:
919 case 3:

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938 grant = r;
939 break;
940 default:
941 grant = false;
942 }
943 }
944 break;
945 case EL2:
946 if (checkPAN(tc, ap, req, mode)) {
947 grant = false;
948 break;
949 }
950 M5_FALLTHROUGH;
941 case EL3:
942 {
943 uint8_t perm = (ap & 0x2) | xn;
944 switch (perm) {
945 case 0:
946 grant = r || w || (x && !sctlr.wxn) ;
947 break;
948 case 1:

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984 ArmFault::PermissionLL + te->lookupLevel,
985 isStage2, ArmFault::LpaeTran);
986 }
987 }
988
989 return NoFault;
990}
991
951 case EL3:
952 {
953 uint8_t perm = (ap & 0x2) | xn;
954 switch (perm) {
955 case 0:
956 grant = r || w || (x && !sctlr.wxn) ;
957 break;
958 case 1:

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994 ArmFault::PermissionLL + te->lookupLevel,
995 isStage2, ArmFault::LpaeTran);
996 }
997 }
998
999 return NoFault;
1000}
1001
1002bool
1003TLB::checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode)
1004{
1005 // The PAN bit has no effect on:
1006 // 1) Instruction accesses.
1007 // 2) Data Cache instructions other than DC ZVA
1008 // 3) Address translation instructions, other than ATS1E1RP and
1009 // ATS1E1WP when ARMv8.2-ATS1E1 is implemented. (Unimplemented in
1010 // gem5)
1011 // 4) Unprivileged instructions (Unimplemented in gem5)
1012 AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
1013 if (mmfr1.pan && cpsr.pan && (ap & 0x1) && mode != Execute &&
1014 (!req->isCacheMaintenance() ||
1015 (req->getFlags() & Request::CACHE_BLOCK_ZERO))) {
1016 return true;
1017 } else {
1018 return false;
1019 }
1020}
1021
992Fault
993TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
994 Translation *translation, bool &delay, bool timing,
995 TLB::ArmTranslationType tranType, bool functional)
996{
997 // No such thing as a functional timing access
998 assert(!(timing && functional));
999

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1023TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
1024 Translation *translation, bool &delay, bool timing,
1025 TLB::ArmTranslationType tranType, bool functional)
1026{
1027 // No such thing as a functional timing access
1028 assert(!(timing && functional));
1029

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