tlb.cc (12763:37c243ed1112) tlb.cc (13374:b7f652df5e5b)
1/*
2 * Copyright (c) 2010-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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70#include "sim/full_system.hh"
71#include "sim/process.hh"
72
73using namespace std;
74using namespace ArmISA;
75
76TLB::TLB(const ArmTLBParams *p)
77 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
1/*
2 * Copyright (c) 2010-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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70#include "sim/full_system.hh"
71#include "sim/process.hh"
72
73using namespace std;
74using namespace ArmISA;
75
76TLB::TLB(const ArmTLBParams *p)
77 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
78 isStage2(p->is_stage2), stage2Req(false), _attr(0),
78 isStage2(p->is_stage2), stage2Req(false), stage2DescReq(false), _attr(0),
79 directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
80 stage2Mmu(NULL), test(nullptr), rangeMRU(1),
81 aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
82 isHyp(false), asid(0), vmid(0), dacr(0),
83 miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
84{
85 const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys);
86

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388{
389 TLB *otlb = dynamic_cast<TLB*>(_otlb);
390 /* Make sure we actually have a valid type */
391 if (otlb) {
392 _attr = otlb->_attr;
393 haveLPAE = otlb->haveLPAE;
394 directToStage2 = otlb->directToStage2;
395 stage2Req = otlb->stage2Req;
79 directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
80 stage2Mmu(NULL), test(nullptr), rangeMRU(1),
81 aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
82 isHyp(false), asid(0), vmid(0), dacr(0),
83 miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
84{
85 const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys);
86

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388{
389 TLB *otlb = dynamic_cast<TLB*>(_otlb);
390 /* Make sure we actually have a valid type */
391 if (otlb) {
392 _attr = otlb->_attr;
393 haveLPAE = otlb->haveLPAE;
394 directToStage2 = otlb->directToStage2;
395 stage2Req = otlb->stage2Req;
396 stage2DescReq = otlb->stage2DescReq;
396
397 /* Sync the stage2 MMU if they exist in both
398 * the old CPU and the new
399 */
400 if (!isStage2 &&
401 stage2Tlb && otlb->stage2Tlb) {
402 stage2Tlb->takeOverFrom(otlb->stage2Tlb);
403 }

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410TLB::serialize(CheckpointOut &cp) const
411{
412 DPRINTF(Checkpoint, "Serializing Arm TLB\n");
413
414 SERIALIZE_SCALAR(_attr);
415 SERIALIZE_SCALAR(haveLPAE);
416 SERIALIZE_SCALAR(directToStage2);
417 SERIALIZE_SCALAR(stage2Req);
397
398 /* Sync the stage2 MMU if they exist in both
399 * the old CPU and the new
400 */
401 if (!isStage2 &&
402 stage2Tlb && otlb->stage2Tlb) {
403 stage2Tlb->takeOverFrom(otlb->stage2Tlb);
404 }

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411TLB::serialize(CheckpointOut &cp) const
412{
413 DPRINTF(Checkpoint, "Serializing Arm TLB\n");
414
415 SERIALIZE_SCALAR(_attr);
416 SERIALIZE_SCALAR(haveLPAE);
417 SERIALIZE_SCALAR(directToStage2);
418 SERIALIZE_SCALAR(stage2Req);
419 SERIALIZE_SCALAR(stage2DescReq);
418
419 int num_entries = size;
420 SERIALIZE_SCALAR(num_entries);
421 for (int i = 0; i < size; i++)
422 table[i].serializeSection(cp, csprintf("TlbEntry%d", i));
423}
424
425void
426TLB::unserialize(CheckpointIn &cp)
427{
428 DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
429
430 UNSERIALIZE_SCALAR(_attr);
431 UNSERIALIZE_SCALAR(haveLPAE);
432 UNSERIALIZE_SCALAR(directToStage2);
433 UNSERIALIZE_SCALAR(stage2Req);
420
421 int num_entries = size;
422 SERIALIZE_SCALAR(num_entries);
423 for (int i = 0; i < size; i++)
424 table[i].serializeSection(cp, csprintf("TlbEntry%d", i));
425}
426
427void
428TLB::unserialize(CheckpointIn &cp)
429{
430 DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
431
432 UNSERIALIZE_SCALAR(_attr);
433 UNSERIALIZE_SCALAR(haveLPAE);
434 UNSERIALIZE_SCALAR(directToStage2);
435 UNSERIALIZE_SCALAR(stage2Req);
436 UNSERIALIZE_SCALAR(stage2DescReq);
434
435 int num_entries;
436 UNSERIALIZE_SCALAR(num_entries);
437 for (int i = 0; i < min(size, num_entries); i++)
438 table[i].unserializeSection(cp, csprintf("TlbEntry%d", i));
439}
440
441void

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1305 isHyp &= (tranType & S1CTran) == 0;
1306 // Work out if we should skip the first stage of translation and go
1307 // directly to stage 2. This value is cached so we don't have to
1308 // compute it for every translation.
1309 stage2Req = isStage2 ||
1310 (hcr.vm && !isHyp && !isSecure &&
1311 !(tranType & S1CTran) && (aarch64EL < EL2) &&
1312 !(tranType & S1E1Tran)); // <--- FIX THIS HACK
437
438 int num_entries;
439 UNSERIALIZE_SCALAR(num_entries);
440 for (int i = 0; i < min(size, num_entries); i++)
441 table[i].unserializeSection(cp, csprintf("TlbEntry%d", i));
442}
443
444void

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1308 isHyp &= (tranType & S1CTran) == 0;
1309 // Work out if we should skip the first stage of translation and go
1310 // directly to stage 2. This value is cached so we don't have to
1311 // compute it for every translation.
1312 stage2Req = isStage2 ||
1313 (hcr.vm && !isHyp && !isSecure &&
1314 !(tranType & S1CTran) && (aarch64EL < EL2) &&
1315 !(tranType & S1E1Tran)); // <--- FIX THIS HACK
1316 stage2DescReq = isStage2 || (hcr.vm && !isHyp && !isSecure &&
1317 (aarch64EL < EL2));
1313 directToStage2 = !isStage2 && stage2Req && !sctlr.m;
1314 } else {
1315 vmid = 0;
1316 isHyp = false;
1317 directToStage2 = false;
1318 stage2Req = false;
1318 directToStage2 = !isStage2 && stage2Req && !sctlr.m;
1319 } else {
1320 vmid = 0;
1321 isHyp = false;
1322 directToStage2 = false;
1323 stage2Req = false;
1324 stage2DescReq = false;
1319 }
1320 } else { // AArch32
1321 sctlr = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc,
1322 !isSecure));
1323 ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc,
1324 !isSecure));
1325 scr = tc->readMiscReg(MISCREG_SCR);
1326 isPriv = cpsr.mode != MODE_USER;

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1352 if (isHyp) {
1353 sctlr = tc->readMiscReg(MISCREG_HSCTLR);
1354 }
1355 // Work out if we should skip the first stage of translation and go
1356 // directly to stage 2. This value is cached so we don't have to
1357 // compute it for every translation.
1358 stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure &&
1359 !(tranType & S1CTran);
1325 }
1326 } else { // AArch32
1327 sctlr = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc,
1328 !isSecure));
1329 ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc,
1330 !isSecure));
1331 scr = tc->readMiscReg(MISCREG_SCR);
1332 isPriv = cpsr.mode != MODE_USER;

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1358 if (isHyp) {
1359 sctlr = tc->readMiscReg(MISCREG_HSCTLR);
1360 }
1361 // Work out if we should skip the first stage of translation and go
1362 // directly to stage 2. This value is cached so we don't have to
1363 // compute it for every translation.
1364 stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure &&
1365 !(tranType & S1CTran);
1366 stage2DescReq = hcr.vm && !isStage2 && !isHyp && !isSecure;
1360 directToStage2 = stage2Req && !sctlr.m;
1361 } else {
1362 vmid = 0;
1363 stage2Req = false;
1364 isHyp = false;
1365 directToStage2 = false;
1367 directToStage2 = stage2Req && !sctlr.m;
1368 } else {
1369 vmid = 0;
1370 stage2Req = false;
1371 isHyp = false;
1372 directToStage2 = false;
1373 stage2DescReq = false;
1366 }
1367 }
1368 miscRegValid = true;
1369 miscRegContext = tc->contextId();
1370 curTranType = tranType;
1371}
1372
1373ExceptionLevel

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1435
1436 // start translation table walk, pass variables rather than
1437 // re-retreaving in table walker for speed
1438 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n",
1439 vaddr_tainted, asid, vmid);
1440 Fault fault;
1441 fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode,
1442 translation, timing, functional, is_secure,
1374 }
1375 }
1376 miscRegValid = true;
1377 miscRegContext = tc->contextId();
1378 curTranType = tranType;
1379}
1380
1381ExceptionLevel

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1443
1444 // start translation table walk, pass variables rather than
1445 // re-retreaving in table walker for speed
1446 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n",
1447 vaddr_tainted, asid, vmid);
1448 Fault fault;
1449 fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode,
1450 translation, timing, functional, is_secure,
1443 tranType, stage2Req);
1451 tranType, stage2DescReq);
1444 // for timing mode, return and wait for table walk,
1445 if (timing || fault != NoFault) {
1446 return fault;
1447 }
1448
1449 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el);
1450 if (!*te)
1451 printTlb();

--- 126 unchanged lines hidden --- 		1452 // for timing mode, return and wait for table walk,
1453 if (timing || fault != NoFault) {
1454 return fault;
1455 }
1456
1457 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el);
1458 if (!*te)
1459 printTlb();

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