tlb.cc (12735:e3da526a0654) | tlb.cc (12749:223c83ed9979) |
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1/* 2 * Copyright (c) 2010-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 119 unchanged lines hidden (view full) --- 128 aarch64 ? aarch64EL : EL1); 129 if (!e) 130 return false; 131 pa = e->pAddr(va); 132 return true; 133} 134 135Fault | 1/* 2 * Copyright (c) 2010-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 119 unchanged lines hidden (view full) --- 128 aarch64 ? aarch64EL : EL1); 129 if (!e) 130 return false; 131 pa = e->pAddr(va); 132 return true; 133} 134 135Fault |
136TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const | 136TLB::finalizePhysical(const RequestPtr &req, 137 ThreadContext *tc, Mode mode) const |
137{ 138 const Addr paddr = req->getPaddr(); 139 140 if (m5opRange.contains(paddr)) { 141 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); 142 req->setPaddr(GenericISA::iprAddressPseudoInst( 143 (paddr >> 8) & 0xFF, 144 paddr & 0xFF)); --- 411 unchanged lines hidden (view full) --- 556 557void 558TLB::regProbePoints() 559{ 560 ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills")); 561} 562 563Fault | 138{ 139 const Addr paddr = req->getPaddr(); 140 141 if (m5opRange.contains(paddr)) { 142 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); 143 req->setPaddr(GenericISA::iprAddressPseudoInst( 144 (paddr >> 8) & 0xFF, 145 paddr & 0xFF)); --- 411 unchanged lines hidden (view full) --- 557 558void 559TLB::regProbePoints() 560{ 561 ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills")); 562} 563 564Fault |
564TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, | 565TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, |
565 Translation *translation, bool &delay, bool timing) 566{ 567 updateMiscReg(tc); 568 Addr vaddr_tainted = req->getVaddr(); 569 Addr vaddr = 0; 570 if (aarch64) 571 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 572 else --- 23 unchanged lines hidden (view full) --- 596 if (!p->pTable->translate(vaddr, paddr)) 597 return std::make_shared<GenericPageTableFault>(vaddr_tainted); 598 req->setPaddr(paddr); 599 600 return finalizePhysical(req, tc, mode); 601} 602 603Fault | 566 Translation *translation, bool &delay, bool timing) 567{ 568 updateMiscReg(tc); 569 Addr vaddr_tainted = req->getVaddr(); 570 Addr vaddr = 0; 571 if (aarch64) 572 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 573 else --- 23 unchanged lines hidden (view full) --- 597 if (!p->pTable->translate(vaddr, paddr)) 598 return std::make_shared<GenericPageTableFault>(vaddr_tainted); 599 req->setPaddr(paddr); 600 601 return finalizePhysical(req, tc, mode); 602} 603 604Fault |
604TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) | 605TLB::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode) |
605{ 606 // a data cache maintenance instruction that operates by MVA does 607 // not generate a Data Abort exeception due to a Permission fault 608 if (req->isCacheMaintenance()) { 609 return NoFault; 610 } 611 612 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify --- 161 unchanged lines hidden (view full) --- 774 ArmFault::PermissionLL + te->lookupLevel, 775 isStage2 | !abt, tranMethod); 776 } 777 return NoFault; 778} 779 780 781Fault | 606{ 607 // a data cache maintenance instruction that operates by MVA does 608 // not generate a Data Abort exeception due to a Permission fault 609 if (req->isCacheMaintenance()) { 610 return NoFault; 611 } 612 613 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify --- 161 unchanged lines hidden (view full) --- 775 ArmFault::PermissionLL + te->lookupLevel, 776 isStage2 | !abt, tranMethod); 777 } 778 return NoFault; 779} 780 781 782Fault |
782TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, | 783TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, |
783 ThreadContext *tc) 784{ 785 assert(aarch64); 786 787 // A data cache maintenance instruction that operates by VA does 788 // not generate a Permission fault unless: 789 // * It is a data cache invalidate (dc ivac) which requires write 790 // permissions to the VA, or --- 193 unchanged lines hidden (view full) --- 984 isStage2, ArmFault::LpaeTran); 985 } 986 } 987 988 return NoFault; 989} 990 991Fault | 784 ThreadContext *tc) 785{ 786 assert(aarch64); 787 788 // A data cache maintenance instruction that operates by VA does 789 // not generate a Permission fault unless: 790 // * It is a data cache invalidate (dc ivac) which requires write 791 // permissions to the VA, or --- 193 unchanged lines hidden (view full) --- 985 isStage2, ArmFault::LpaeTran); 986 } 987 } 988 989 return NoFault; 990} 991 992Fault |
992TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, | 993TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, |
993 Translation *translation, bool &delay, bool timing, 994 TLB::ArmTranslationType tranType, bool functional) 995{ 996 // No such thing as a functional timing access 997 assert(!(timing && functional)); 998 999 updateMiscReg(tc, tranType); 1000 --- 152 unchanged lines hidden (view full) --- 1153 // translation has completed (i.e., there is a table entry). 1154 return te ? finalizePhysical(req, tc, mode) : NoFault; 1155 } else { 1156 return fault; 1157 } 1158} 1159 1160Fault | 994 Translation *translation, bool &delay, bool timing, 995 TLB::ArmTranslationType tranType, bool functional) 996{ 997 // No such thing as a functional timing access 998 assert(!(timing && functional)); 999 1000 updateMiscReg(tc, tranType); 1001 --- 152 unchanged lines hidden (view full) --- 1154 // translation has completed (i.e., there is a table entry). 1155 return te ? finalizePhysical(req, tc, mode) : NoFault; 1156 } else { 1157 return fault; 1158 } 1159} 1160 1161Fault |
1161TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, | 1162TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, |
1162 TLB::ArmTranslationType tranType) 1163{ 1164 updateMiscReg(tc, tranType); 1165 1166 if (directToStage2) { 1167 assert(stage2Tlb); 1168 return stage2Tlb->translateAtomic(req, tc, mode, tranType); 1169 } --- 4 unchanged lines hidden (view full) --- 1174 fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 1175 else 1176 fault = translateSe(req, tc, mode, NULL, delay, false); 1177 assert(!delay); 1178 return fault; 1179} 1180 1181Fault | 1163 TLB::ArmTranslationType tranType) 1164{ 1165 updateMiscReg(tc, tranType); 1166 1167 if (directToStage2) { 1168 assert(stage2Tlb); 1169 return stage2Tlb->translateAtomic(req, tc, mode, tranType); 1170 } --- 4 unchanged lines hidden (view full) --- 1175 fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 1176 else 1177 fault = translateSe(req, tc, mode, NULL, delay, false); 1178 assert(!delay); 1179 return fault; 1180} 1181 1182Fault |
1182TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, | 1183TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode, |
1183 TLB::ArmTranslationType tranType) 1184{ 1185 updateMiscReg(tc, tranType); 1186 1187 if (directToStage2) { 1188 assert(stage2Tlb); 1189 return stage2Tlb->translateFunctional(req, tc, mode, tranType); 1190 } --- 4 unchanged lines hidden (view full) --- 1195 fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 1196 else 1197 fault = translateSe(req, tc, mode, NULL, delay, false); 1198 assert(!delay); 1199 return fault; 1200} 1201 1202void | 1184 TLB::ArmTranslationType tranType) 1185{ 1186 updateMiscReg(tc, tranType); 1187 1188 if (directToStage2) { 1189 assert(stage2Tlb); 1190 return stage2Tlb->translateFunctional(req, tc, mode, tranType); 1191 } --- 4 unchanged lines hidden (view full) --- 1196 fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 1197 else 1198 fault = translateSe(req, tc, mode, NULL, delay, false); 1199 assert(!delay); 1200 return fault; 1201} 1202 1203void |
1203TLB::translateTiming(RequestPtr req, ThreadContext *tc, | 1204TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, |
1204 Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 1205{ 1206 updateMiscReg(tc, tranType); 1207 1208 if (directToStage2) { 1209 assert(stage2Tlb); 1210 stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 1211 return; 1212 } 1213 1214 assert(translation); 1215 1216 translateComplete(req, tc, translation, mode, tranType, isStage2); 1217} 1218 1219Fault | 1205 Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 1206{ 1207 updateMiscReg(tc, tranType); 1208 1209 if (directToStage2) { 1210 assert(stage2Tlb); 1211 stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 1212 return; 1213 } 1214 1215 assert(translation); 1216 1217 translateComplete(req, tc, translation, mode, tranType, isStage2); 1218} 1219 1220Fault |
1220TLB::translateComplete(RequestPtr req, ThreadContext *tc, | 1221TLB::translateComplete(const RequestPtr &req, ThreadContext *tc, |
1221 Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 1222 bool callFromS2) 1223{ 1224 bool delay = false; 1225 Fault fault; 1226 if (FullSystem) 1227 fault = translateFs(req, tc, mode, translation, delay, true, tranType); 1228 else --- 170 unchanged lines hidden (view full) --- 1399 return opModeToEL((OperatingMode)(uint8_t)cpsr.mode); 1400 1401 default: 1402 panic("Unknown translation mode!\n"); 1403 } 1404} 1405 1406Fault | 1222 Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 1223 bool callFromS2) 1224{ 1225 bool delay = false; 1226 Fault fault; 1227 if (FullSystem) 1228 fault = translateFs(req, tc, mode, translation, delay, true, tranType); 1229 else --- 170 unchanged lines hidden (view full) --- 1400 return opModeToEL((OperatingMode)(uint8_t)cpsr.mode); 1401 1402 default: 1403 panic("Unknown translation mode!\n"); 1404 } 1405} 1406 1407Fault |
1407TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, | 1408TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, |
1408 Translation *translation, bool timing, bool functional, 1409 bool is_secure, TLB::ArmTranslationType tranType) 1410{ 1411 bool is_fetch = (mode == Execute); 1412 bool is_write = (mode == Write); 1413 1414 Addr vaddr_tainted = req->getVaddr(); 1415 Addr vaddr = 0; --- 45 unchanged lines hidden (view full) --- 1461 writeHits++; 1462 else 1463 readHits++; 1464 } 1465 return NoFault; 1466} 1467 1468Fault | 1409 Translation *translation, bool timing, bool functional, 1410 bool is_secure, TLB::ArmTranslationType tranType) 1411{ 1412 bool is_fetch = (mode == Execute); 1413 bool is_write = (mode == Write); 1414 1415 Addr vaddr_tainted = req->getVaddr(); 1416 Addr vaddr = 0; --- 45 unchanged lines hidden (view full) --- 1462 writeHits++; 1463 else 1464 readHits++; 1465 } 1466 return NoFault; 1467} 1468 1469Fault |
1469TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, | 1470TLB::getResultTe(TlbEntry **te, const RequestPtr &req, 1471 ThreadContext *tc, Mode mode, |
1470 Translation *translation, bool timing, bool functional, 1471 TlbEntry *mergeTe) 1472{ 1473 Fault fault; 1474 1475 if (isStage2) { 1476 // We are already in the stage 2 TLB. Grab the table entry for stage 1477 // 2 only. We are here because stage 1 translation is disabled. --- 66 unchanged lines hidden (view full) --- 1544 } else { 1545 TlbTestInterface *ti(dynamic_cast<TlbTestInterface *>(_ti)); 1546 fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name()); 1547 test = ti; 1548 } 1549} 1550 1551Fault | 1472 Translation *translation, bool timing, bool functional, 1473 TlbEntry *mergeTe) 1474{ 1475 Fault fault; 1476 1477 if (isStage2) { 1478 // We are already in the stage 2 TLB. Grab the table entry for stage 1479 // 2 only. We are here because stage 1 translation is disabled. --- 66 unchanged lines hidden (view full) --- 1546 } else { 1547 TlbTestInterface *ti(dynamic_cast<TlbTestInterface *>(_ti)); 1548 fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name()); 1549 test = ti; 1550 } 1551} 1552 1553Fault |
1552TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) | 1554TLB::testTranslation(const RequestPtr &req, Mode mode, 1555 TlbEntry::DomainType domain) |
1553{ 1554 if (!test || !req->hasSize() || req->getSize() == 0 || 1555 req->isCacheMaintenance()) { 1556 return NoFault; 1557 } else { 1558 return test->translationCheck(req, isPriv, mode, domain); 1559 } 1560} --- 19 unchanged lines hidden --- | 1556{ 1557 if (!test || !req->hasSize() || req->getSize() == 0 || 1558 req->isCacheMaintenance()) { 1559 return NoFault; 1560 } else { 1561 return test->translationCheck(req, isPriv, mode, domain); 1562 } 1563} --- 19 unchanged lines hidden --- |