tlb.cc (11861:9684637f3339) tlb.cc (12005:f4b9607db0af)
1/*
2 * Copyright (c) 2010-2013, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50
51#include "arch/arm/faults.hh"
52#include "arch/arm/pagetable.hh"
53#include "arch/arm/stage2_lookup.hh"
54#include "arch/arm/stage2_mmu.hh"
55#include "arch/arm/system.hh"
56#include "arch/arm/table_walker.hh"
57#include "arch/arm/utility.hh"
1/*
2 * Copyright (c) 2010-2013, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50
51#include "arch/arm/faults.hh"
52#include "arch/arm/pagetable.hh"
53#include "arch/arm/stage2_lookup.hh"
54#include "arch/arm/stage2_mmu.hh"
55#include "arch/arm/system.hh"
56#include "arch/arm/table_walker.hh"
57#include "arch/arm/utility.hh"
58#include "arch/generic/mmapped_ipr.hh"
58#include "base/inifile.hh"
59#include "base/str.hh"
60#include "base/trace.hh"
61#include "cpu/base.hh"
62#include "cpu/thread_context.hh"
63#include "debug/Checkpoint.hh"
64#include "debug/TLB.hh"
65#include "debug/TLBVerbose.hh"

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76 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
77 isStage2(p->is_stage2), stage2Req(false), _attr(0),
78 directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
79 stage2Mmu(NULL), test(nullptr), rangeMRU(1),
80 aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
81 isHyp(false), asid(0), vmid(0), dacr(0),
82 miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
83{
59#include "base/inifile.hh"
60#include "base/str.hh"
61#include "base/trace.hh"
62#include "cpu/base.hh"
63#include "cpu/thread_context.hh"
64#include "debug/Checkpoint.hh"
65#include "debug/TLB.hh"
66#include "debug/TLBVerbose.hh"

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77 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
78 isStage2(p->is_stage2), stage2Req(false), _attr(0),
79 directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
80 stage2Mmu(NULL), test(nullptr), rangeMRU(1),
81 aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
82 isHyp(false), asid(0), vmid(0), dacr(0),
83 miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
84{
85 const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys);
86
84 tableWalker->setTlb(this);
85
86 // Cache system-level properties
87 haveLPAE = tableWalker->haveLPAE();
88 haveVirtualization = tableWalker->haveVirtualization();
89 haveLargeAsid64 = tableWalker->haveLargeAsid64();
87 tableWalker->setTlb(this);
88
89 // Cache system-level properties
90 haveLPAE = tableWalker->haveLPAE();
91 haveVirtualization = tableWalker->haveVirtualization();
92 haveLargeAsid64 = tableWalker->haveLargeAsid64();
93
94 if (sys)
95 m5opRange = sys->m5opRange();
90}
91
92TLB::~TLB()
93{
94 delete[] table;
95}
96
97void

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124 return false;
125 pa = e->pAddr(va);
126 return true;
127}
128
129Fault
130TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
131{
96}
97
98TLB::~TLB()
99{
100 delete[] table;
101}
102
103void

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130 return false;
131 pa = e->pAddr(va);
132 return true;
133}
134
135Fault
136TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
137{
138 const Addr paddr = req->getPaddr();
139
140 if (m5opRange.contains(paddr)) {
141 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
142 req->setPaddr(GenericISA::iprAddressPseudoInst(
143 (paddr >> 8) & 0xFF,
144 paddr & 0xFF));
145 }
146
132 return NoFault;
133}
134
135TlbEntry*
136TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
137 bool functional, bool ignore_asn, uint8_t target_el)
138{
139

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577
578 Addr paddr;
579 Process *p = tc->getProcessPtr();
580
581 if (!p->pTable->translate(vaddr, paddr))
582 return std::make_shared<GenericPageTableFault>(vaddr_tainted);
583 req->setPaddr(paddr);
584
147 return NoFault;
148}
149
150TlbEntry*
151TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
152 bool functional, bool ignore_asn, uint8_t target_el)
153{
154

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592
593 Addr paddr;
594 Process *p = tc->getProcessPtr();
595
596 if (!p->pTable->translate(vaddr, paddr))
597 return std::make_shared<GenericPageTableFault>(vaddr_tainted);
598 req->setPaddr(paddr);
599
585 return NoFault;
600 return finalizePhysical(req, tc, mode);
586}
587
588Fault
589TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
590{
591 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
592 Request::Flags flags = req->getFlags();
593 bool is_fetch = (mode == Execute);

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1103 tranMethod);
1104 }
1105
1106 // Check for a trickbox generated address fault
1107 if (fault == NoFault)
1108 fault = testTranslation(req, mode, te->domain);
1109 }
1110
601}
602
603Fault
604TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
605{
606 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
607 Request::Flags flags = req->getFlags();
608 bool is_fetch = (mode == Execute);

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1118 tranMethod);
1119 }
1120
1121 // Check for a trickbox generated address fault
1122 if (fault == NoFault)
1123 fault = testTranslation(req, mode, te->domain);
1124 }
1125
1111 // Generate Illegal Inst Set State fault if IL bit is set in CPSR
1112 if (fault == NoFault) {
1126 if (fault == NoFault) {
1127 // Generate Illegal Inst Set State fault if IL bit is set in CPSR
1113 if (aarch64 && is_fetch && cpsr.il == 1) {
1114 return std::make_shared<IllegalInstSetStateFault>();
1115 }
1128 if (aarch64 && is_fetch && cpsr.il == 1) {
1129 return std::make_shared<IllegalInstSetStateFault>();
1130 }
1116 }
1117
1131
1118 return fault;
1132 // Don't try to finalize a physical address unless the
1133 // translation has completed (i.e., there is a table entry).
1134 return te ? finalizePhysical(req, tc, mode) : NoFault;
1135 } else {
1136 return fault;
1137 }
1119}
1120
1121Fault
1122TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
1123 TLB::ArmTranslationType tranType)
1124{
1125 updateMiscReg(tc, tranType);
1126

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1139
1140Fault
1141TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
1142 TLB::ArmTranslationType tranType)
1143{
1144 updateMiscReg(tc, tranType);
1145

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