tlb.cc (11505:55256a05d9e9) tlb.cc (11517:54230f1ebef2)
1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 937 unchanged lines hidden (view full) ---

946 if (aarch64)
947 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
948 else
949 vaddr = vaddr_tainted;
950 uint32_t flags = req->getFlags();
951
952 bool is_fetch = (mode == Execute);
953 bool is_write = (mode == Write);
1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 937 unchanged lines hidden (view full) ---

946 if (aarch64)
947 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
948 else
949 vaddr = vaddr_tainted;
950 uint32_t flags = req->getFlags();
951
952 bool is_fetch = (mode == Execute);
953 bool is_write = (mode == Write);
954 bool long_desc_format = aarch64 || (haveLPAE && ttbcr.eae);
954 bool long_desc_format = aarch64 || longDescFormatInUse(tc);
955 ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran
956 : ArmFault::VmsaTran;
957
958 req->setAsid(asid);
959
960 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n",
961 isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran);
962

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1242 stage2Req = false;
1243 } else { // AArch32
1244 sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc,
1245 !isSecure));
1246 ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc,
1247 !isSecure));
1248 scr = tc->readMiscReg(MISCREG_SCR);
1249 isPriv = cpsr.mode != MODE_USER;
955 ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran
956 : ArmFault::VmsaTran;
957
958 req->setAsid(asid);
959
960 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n",
961 isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran);
962

--- 279 unchanged lines hidden (view full) ---

1242 stage2Req = false;
1243 } else { // AArch32
1244 sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc,
1245 !isSecure));
1246 ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc,
1247 !isSecure));
1248 scr = tc->readMiscReg(MISCREG_SCR);
1249 isPriv = cpsr.mode != MODE_USER;
1250 if (haveLPAE && ttbcr.eae) {
1251 // Long-descriptor translation table format in use
1250 if (longDescFormatInUse(tc)) {
1252 uint64_t ttbr_asid = tc->readMiscReg(
1253 flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1
1254 : MISCREG_TTBR0,
1255 tc, !isSecure));
1256 asid = bits(ttbr_asid, 55, 48);
1251 uint64_t ttbr_asid = tc->readMiscReg(
1252 flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1
1253 : MISCREG_TTBR0,
1254 tc, !isSecure));
1255 asid = bits(ttbr_asid, 55, 48);
1257 } else {
1258 // Short-descriptor translation table format in use
1256 } else { // Short-descriptor translation table format in use
1259 CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked(
1260 MISCREG_CONTEXTIDR, tc,!isSecure));
1261 asid = context_id.asid;
1262 }
1263 prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc,
1264 !isSecure));
1265 nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc,
1266 !isSecure));

--- 185 unchanged lines hidden --- 		1257 CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked(
1258 MISCREG_CONTEXTIDR, tc,!isSecure));
1259 asid = context_id.asid;
1260 }
1261 prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc,
1262 !isSecure));
1263 nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc,
1264 !isSecure));

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