tlb.cc (11495:1f04f97c014d) tlb.cc (11505:55256a05d9e9)
1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1183 unchanged lines hidden (view full) ---

1192 // one type of translation anyway
1193 if (miscRegValid && miscRegContext == tc->contextId() &&
1194 ((tranType == curTranType) || isStage2)) {
1195 return;
1196 }
1197
1198 DPRINTF(TLBVerbose, "TLB variables changed!\n");
1199 cpsr = tc->readMiscReg(MISCREG_CPSR);
1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1183 unchanged lines hidden (view full) ---

1192 // one type of translation anyway
1193 if (miscRegValid && miscRegContext == tc->contextId() &&
1194 ((tranType == curTranType) || isStage2)) {
1195 return;
1196 }
1197
1198 DPRINTF(TLBVerbose, "TLB variables changed!\n");
1199 cpsr = tc->readMiscReg(MISCREG_CPSR);
1200
1200 // Dependencies: SCR/SCR_EL3, CPSR
1201 // Dependencies: SCR/SCR_EL3, CPSR
1201 isSecure = inSecureState(tc);
1202 isSecure &= (tranType & HypMode) == 0;
1203 isSecure &= (tranType & S1S2NsTran) == 0;
1204 aarch64 = !cpsr.width;
1202 isSecure = inSecureState(tc) &&
1203 !(tranType & HypMode) && !(tranType & S1S2NsTran);
1204
1205 const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode;
1206 aarch64 = opModeIs64(op_mode) ||
1207 (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1));
1208
1205 if (aarch64) { // AArch64
1206 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
1207 switch (aarch64EL) {
1208 case EL0:
1209 case EL1:
1210 {
1211 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1212 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1);

--- 235 unchanged lines hidden --- 		1209 if (aarch64) { // AArch64
1210 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
1211 switch (aarch64EL) {
1212 case EL0:
1213 case EL1:
1214 {
1215 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1216 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1);

--- 235 unchanged lines hidden ---