tlb.cc (10825:5d059b8ed8a4) tlb.cc (10854:f449d6f8a647)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 532 unchanged lines hidden (view full) ---

541Fault
542TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
543 Translation *translation, bool &delay, bool timing)
544{
545 updateMiscReg(tc);
546 Addr vaddr_tainted = req->getVaddr();
547 Addr vaddr = 0;
548 if (aarch64)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 532 unchanged lines hidden (view full) ---

541Fault
542TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
543 Translation *translation, bool &delay, bool timing)
544{
545 updateMiscReg(tc);
546 Addr vaddr_tainted = req->getVaddr();
547 Addr vaddr = 0;
548 if (aarch64)
549 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL);
549 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
550 else
551 vaddr = vaddr_tainted;
552 uint32_t flags = req->getFlags();
553
554 bool is_fetch = (mode == Execute);
555 bool is_write = (mode == Write);
556
557 if (!is_fetch) {

--- 202 unchanged lines hidden (view full) ---

760
761Fault
762TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
763 ThreadContext *tc)
764{
765 assert(aarch64);
766
767 Addr vaddr_tainted = req->getVaddr();
550 else
551 vaddr = vaddr_tainted;
552 uint32_t flags = req->getFlags();
553
554 bool is_fetch = (mode == Execute);
555 bool is_write = (mode == Write);
556
557 if (!is_fetch) {

--- 202 unchanged lines hidden (view full) ---

760
761Fault
762TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
763 ThreadContext *tc)
764{
765 assert(aarch64);
766
767 Addr vaddr_tainted = req->getVaddr();
768 Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL);
768 Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
769
770 uint32_t flags = req->getFlags();
771 bool is_fetch = (mode == Execute);
772 bool is_write = (mode == Write);
773 bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode);
774
775 updateMiscReg(tc, curTranType);
776

--- 177 unchanged lines hidden (view full) ---

954 // No such thing as a functional timing access
955 assert(!(timing && functional));
956
957 updateMiscReg(tc, tranType);
958
959 Addr vaddr_tainted = req->getVaddr();
960 Addr vaddr = 0;
961 if (aarch64)
769
770 uint32_t flags = req->getFlags();
771 bool is_fetch = (mode == Execute);
772 bool is_write = (mode == Write);
773 bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode);
774
775 updateMiscReg(tc, curTranType);
776

--- 177 unchanged lines hidden (view full) ---

954 // No such thing as a functional timing access
955 assert(!(timing && functional));
956
957 updateMiscReg(tc, tranType);
958
959 Addr vaddr_tainted = req->getVaddr();
960 Addr vaddr = 0;
961 if (aarch64)
962 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL);
962 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
963 else
964 vaddr = vaddr_tainted;
965 uint32_t flags = req->getFlags();
966
967 bool is_fetch = (mode == Execute);
968 bool is_write = (mode == Write);
969 bool long_desc_format = aarch64 || (haveLPAE && ttbcr.eae);
970 ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran

--- 134 unchanged lines hidden (view full) ---

1105 // Check for a trickbox generated address fault
1106 if (fault == NoFault) {
1107 fault = trickBoxCheck(req, mode, te->domain);
1108 }
1109 }
1110
1111 // Generate Illegal Inst Set State fault if IL bit is set in CPSR
1112 if (fault == NoFault) {
963 else
964 vaddr = vaddr_tainted;
965 uint32_t flags = req->getFlags();
966
967 bool is_fetch = (mode == Execute);
968 bool is_write = (mode == Write);
969 bool long_desc_format = aarch64 || (haveLPAE && ttbcr.eae);
970 ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran

--- 134 unchanged lines hidden (view full) ---

1105 // Check for a trickbox generated address fault
1106 if (fault == NoFault) {
1107 fault = trickBoxCheck(req, mode, te->domain);
1108 }
1109 }
1110
1111 // Generate Illegal Inst Set State fault if IL bit is set in CPSR
1112 if (fault == NoFault) {
1113 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1114 if (aarch64 && is_fetch && cpsr.il == 1) {
1115 return std::make_shared<IllegalInstSetStateFault>();
1116 }
1117 }
1118
1119 return fault;
1120}
1121

--- 95 unchanged lines hidden (view full) ---

1217 // check if the regs have changed, or the translation mode is different.
1218 // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
1219 // one type of translation anyway
1220 if (miscRegValid && ((tranType == curTranType) || isStage2)) {
1221 return;
1222 }
1223
1224 DPRINTF(TLBVerbose, "TLB variables changed!\n");
1113 if (aarch64 && is_fetch && cpsr.il == 1) {
1114 return std::make_shared<IllegalInstSetStateFault>();
1115 }
1116 }
1117
1118 return fault;
1119}
1120

--- 95 unchanged lines hidden (view full) ---

1216 // check if the regs have changed, or the translation mode is different.
1217 // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
1218 // one type of translation anyway
1219 if (miscRegValid && ((tranType == curTranType) || isStage2)) {
1220 return;
1221 }
1222
1223 DPRINTF(TLBVerbose, "TLB variables changed!\n");
1225 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1224 cpsr = tc->readMiscReg(MISCREG_CPSR);
1226 // Dependencies: SCR/SCR_EL3, CPSR
1227 isSecure = inSecureState(tc);
1228 isSecure &= (tranType & HypMode) == 0;
1229 isSecure &= (tranType & S1S2NsTran) == 0;
1230 aarch64 = !cpsr.width;
1231 if (aarch64) { // AArch64
1232 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
1233 switch (aarch64EL) {

--- 89 unchanged lines hidden (view full) ---

1323{
1324 bool is_fetch = (mode == Execute);
1325 bool is_write = (mode == Write);
1326
1327 Addr vaddr_tainted = req->getVaddr();
1328 Addr vaddr = 0;
1329 ExceptionLevel target_el = aarch64 ? aarch64EL : EL1;
1330 if (aarch64) {
1225 // Dependencies: SCR/SCR_EL3, CPSR
1226 isSecure = inSecureState(tc);
1227 isSecure &= (tranType & HypMode) == 0;
1228 isSecure &= (tranType & S1S2NsTran) == 0;
1229 aarch64 = !cpsr.width;
1230 if (aarch64) { // AArch64
1231 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
1232 switch (aarch64EL) {

--- 89 unchanged lines hidden (view full) ---

1322{
1323 bool is_fetch = (mode == Execute);
1324 bool is_write = (mode == Write);
1325
1326 Addr vaddr_tainted = req->getVaddr();
1327 Addr vaddr = 0;
1328 ExceptionLevel target_el = aarch64 ? aarch64EL : EL1;
1329 if (aarch64) {
1331 vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el);
1330 vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el, ttbcr);
1332 } else {
1333 vaddr = vaddr_tainted;
1334 }
1335 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el);
1336 if (*te == NULL) {
1337 if (req->isPrefetch()) {
1338 // if the request is a prefetch don't attempt to fill the TLB or go
1339 // any further with the memory access (here we can safely use the

--- 98 unchanged lines hidden --- 		1331 } else {
1332 vaddr = vaddr_tainted;
1333 }
1334 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el);
1335 if (*te == NULL) {
1336 if (req->isPrefetch()) {
1337 // if the request is a prefetch don't attempt to fill the TLB or go
1338 // any further with the memory access (here we can safely use the

--- 98 unchanged lines hidden ---