tlb.cc (10037:5cac77888310) | tlb.cc (10194:e6d2e8083d9c) |
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1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 340 unchanged lines hidden (view full) --- 349TLB::drainResume() 350{ 351 // We might have unserialized something or switched CPUs, so make 352 // sure to re-read the misc regs. 353 miscRegValid = false; 354} 355 356void | 1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 340 unchanged lines hidden (view full) --- 349TLB::drainResume() 350{ 351 // We might have unserialized something or switched CPUs, so make 352 // sure to re-read the misc regs. 353 miscRegValid = false; 354} 355 356void |
357TLB::takeOverFrom(BaseTLB *_otlb) 358{ 359 TLB *otlb = dynamic_cast<TLB*>(_otlb); 360 /* Make sure we actually have a valid type */ 361 if (otlb) { 362 _attr = otlb->_attr; 363 haveLPAE = otlb->haveLPAE; 364 directToStage2 = otlb->directToStage2; 365 stage2Req = otlb->stage2Req; 366 bootUncacheability = otlb->bootUncacheability; 367 368 /* Sync the stage2 MMU if they exist in both 369 * the old CPU and the new 370 */ 371 if (!isStage2 && 372 stage2Tlb && otlb->stage2Tlb) { 373 stage2Tlb->takeOverFrom(otlb->stage2Tlb); 374 } 375 } else { 376 panic("Incompatible TLB type!"); 377 } 378} 379 380void |
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357TLB::serialize(ostream &os) 358{ 359 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 360 361 SERIALIZE_SCALAR(_attr); 362 SERIALIZE_SCALAR(haveLPAE); 363 SERIALIZE_SCALAR(directToStage2); 364 SERIALIZE_SCALAR(stage2Req); --- 1033 unchanged lines hidden --- | 381TLB::serialize(ostream &os) 382{ 383 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 384 385 SERIALIZE_SCALAR(_attr); 386 SERIALIZE_SCALAR(haveLPAE); 387 SERIALIZE_SCALAR(directToStage2); 388 SERIALIZE_SCALAR(stage2Req); --- 1033 unchanged lines hidden --- |