1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 346 unchanged lines hidden (view full) --- 355 356 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 357 & UserMode); 358 // If this is a clrex instruction, provide a PA of 0 with no fault 359 // This will force the monitor to set the tracked address to 0 360 // a bit of a hack but this effectively clrears this processors monitor 361 if (flags & Clrex){ 362 req->setPaddr(0); |
363 req->setFlags(Request::UNCACHEABLE); |
364 return NoFault; 365 } 366 if (!is_fetch) { 367 assert(flags & MustBeOne); 368 if (sctlr.a || !(flags & AllowUnaligned)) { 369 if (vaddr & flags & AlignmentMask) { 370 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 371 } --- 54 unchanged lines hidden (view full) --- 426 } 427 428 // Set memory attributes 429 DPRINTF(TLBVerbose, 430 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 431 outerAttrs: %d\n", 432 te->shareable, te->innerAttrs, te->outerAttrs); 433 setAttr(te->attributes); |
434 if (te->nonCacheable) 435 req->setFlags(Request::UNCACHEABLE); |
436 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 437 switch ( (dacr >> (te->domain * 2)) & 0x3) { 438 case 0: 439 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 440 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 441 if (is_fetch) 442 return new PrefetchAbort(vaddr, 443 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); --- 129 unchanged lines hidden --- |