1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 33 unchanged lines hidden (view full) --- 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" |
50#include "arch/arm/tlb.hh" 51#include "arch/arm/utility.hh" 52#include "base/inifile.hh" 53#include "base/str.hh" 54#include "base/trace.hh" 55#include "cpu/thread_context.hh" 56#include "mem/page_table.hh" 57#include "params/ArmTLB.hh" 58#include "sim/process.hh" 59 |
60#if FULL_SYSTEM 61#include "arch/arm/table_walker.hh" 62#endif 63 |
64using namespace std; 65using namespace ArmISA; 66 67TLB::TLB(const Params *p) 68 : BaseTLB(p), size(p->size), nlu(0) 69#if FULL_SYSTEM 70 , tableWalker(p->walker) 71#endif 72{ 73 table = new TlbEntry[size]; 74 memset(table, 0, sizeof(TlbEntry[size])); 75 |
76#if FULL_SYSTEM |
77 tableWalker->setTlb(this); |
78#endif |
79} 80 81TLB::~TLB() 82{ 83 if (table) 84 delete [] table; 85} 86 --- 205 unchanged lines hidden (view full) --- 292 .desc("DTB accesses") 293 ; 294 295 hits = read_hits + write_hits; 296 misses = read_misses + write_misses; 297 accesses = read_accesses + write_accesses; 298} 299 |
300#if !FULL_SYSTEM 301Fault 302TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 303 Translation *translation, bool &delay, bool timing) 304{ 305 // XXX Cache misc registers and have miscreg write function inv cache 306 Addr vaddr = req->getVaddr() & ~PcModeMask; 307 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); --- 19 unchanged lines hidden (view full) --- 327 req->setPaddr(paddr); 328 329 return NoFault; 330} 331 332#else // FULL_SYSTEM 333 334Fault |
335TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 336{ 337 return NoFault; 338} 339 340Fault 341TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 342 bool is_write, uint8_t domain, bool sNp) 343{ 344 return NoFault; 345} 346 347Fault |
348TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 349 Translation *translation, bool &delay, bool timing) 350{ 351 // XXX Cache misc registers and have miscreg write function inv cache 352 Addr vaddr = req->getVaddr() & ~PcModeMask; 353 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 354 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 355 uint32_t flags = req->getFlags(); --- 79 unchanged lines hidden (view full) --- 435 436 uint8_t ap = te->ap; 437 438 if (sctlr.afe == 1) 439 ap |= 1; 440 441 bool abt; 442 |
443 /* if (!sctlr.xp) 444 ap &= 0x3; 445*/ |
446 switch (ap) { 447 case 0: |
448 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 449 if (!sctlr.xp) { 450 switch ((int)sctlr.rs) { 451 case 2: 452 abt = is_write; 453 break; 454 case 1: 455 abt = is_write || !is_priv; 456 break; 457 case 0: 458 case 3: 459 default: 460 abt = true; 461 break; 462 } 463 } else { 464 abt = true; 465 } |
466 break; 467 case 1: 468 abt = !is_priv; 469 break; 470 case 2: 471 abt = !is_priv && is_write; 472 break; 473 case 3: --- 75 unchanged lines hidden --- |