1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan |
15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the --- 9 unchanged lines hidden (view full) --- 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * |
40 * Authors: Ali Saidi 41 * Nathan Binkert |
42 * Steve Reinhardt |
43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" 50#include "arch/arm/tlb.hh" --- 5 unchanged lines hidden (view full) --- 56#include "mem/page_table.hh" 57#include "params/ArmTLB.hh" 58#include "sim/process.hh" 59 60 61using namespace std; 62using namespace ArmISA; 63 |
64TLB::TLB(const Params *p) 65 : BaseTLB(p), size(p->size), nlu(0) 66{ 67 table = new ArmISA::PTE[size]; 68 memset(table, 0, sizeof(ArmISA::PTE[size])); |
69 |
70} 71 72TLB::~TLB() 73{ 74 if (table) 75 delete [] table; 76} 77 |
78ArmISA::PTE * 79TLB::lookup(Addr vpn, uint8_t asn) const 80{ |
81 panic("lookup() not implemented for ARM\n"); |
82} 83 |
84// insert a new TLB entry 85void 86TLB::insert(Addr addr, ArmISA::PTE &pte) 87{ 88 fatal("TLB Insert not yet implemented\n"); 89} 90 91void --- 18 unchanged lines hidden (view full) --- 110} 111 112void 113TLB::unserialize(Checkpoint *cp, const string §ion) 114{ 115 UNSERIALIZE_SCALAR(size); 116 UNSERIALIZE_SCALAR(nlu); 117 |
118 panic("Need to properly unserialize TLB\n"); |
119 for (int i = 0; i < size; i++) { 120 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); |
121 } 122} 123 124void 125TLB::regStats() 126{ 127 read_hits 128 .name(name() + ".read_hits") --- 94 unchanged lines hidden (view full) --- 223void 224TLB::translateTiming(RequestPtr req, ThreadContext *tc, 225 Translation *translation, Mode mode) 226{ 227 assert(translation); 228 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 229} 230 |
231ArmISA::TLB * 232ArmTLBParams::create() 233{ 234 return new ArmISA::TLB(this); 235} |