1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 50 unchanged lines hidden (view full) --- 59#include "base/str.hh" 60#include "base/trace.hh" 61#include "cpu/base.hh" 62#include "cpu/thread_context.hh" 63#include "debug/Checkpoint.hh" 64#include "debug/TLB.hh" 65#include "debug/TLBVerbose.hh" 66#include "mem/page_table.hh" |
67#include "mem/request.hh" |
68#include "params/ArmTLB.hh" 69#include "sim/full_system.hh" 70#include "sim/process.hh" 71 72using namespace std; 73using namespace ArmISA; 74 75TLB::TLB(const ArmTLBParams *p) --- 475 unchanged lines hidden (view full) --- 551{ 552 updateMiscReg(tc); 553 Addr vaddr_tainted = req->getVaddr(); 554 Addr vaddr = 0; 555 if (aarch64) 556 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 557 else 558 vaddr = vaddr_tainted; |
559 Request::Flags flags = req->getFlags(); |
560 561 bool is_fetch = (mode == Execute); 562 bool is_write = (mode == Write); 563 564 if (!is_fetch) { 565 assert(flags & MustBeOne); 566 if (sctlr.a || !(flags & AllowUnaligned)) { 567 if (vaddr & mask(flags & AlignmentMask)) { --- 16 unchanged lines hidden (view full) --- 584 585 return NoFault; 586} 587 588Fault 589TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 590{ 591 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify |
592 Request::Flags flags = req->getFlags(); |
593 bool is_fetch = (mode == Execute); 594 bool is_write = (mode == Write); 595 bool is_priv = isPriv && !(flags & UserMode); 596 597 // Get the translation type from the actuall table entry 598 ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran 599 : ArmFault::VmsaTran; 600 --- 155 unchanged lines hidden (view full) --- 756TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 757 ThreadContext *tc) 758{ 759 assert(aarch64); 760 761 Addr vaddr_tainted = req->getVaddr(); 762 Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 763 |
764 Request::Flags flags = req->getFlags(); |
765 bool is_fetch = (mode == Execute); 766 bool is_write = (mode == Write); 767 bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 768 769 updateMiscReg(tc, curTranType); 770 771 // If this is the second stage of translation and the request is for a 772 // stage 1 page table walk then we need to check the HCR.PTW bit. This --- 190 unchanged lines hidden (view full) --- 963 updateMiscReg(tc, tranType); 964 965 Addr vaddr_tainted = req->getVaddr(); 966 Addr vaddr = 0; 967 if (aarch64) 968 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 969 else 970 vaddr = vaddr_tainted; |
971 Request::Flags flags = req->getFlags(); |
972 973 bool is_fetch = (mode == Execute); 974 bool is_write = (mode == Write); 975 bool long_desc_format = aarch64 || longDescFormatInUse(tc); 976 ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran 977 : ArmFault::VmsaTran; 978 979 req->setAsid(asid); 980 981 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", 982 isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 983 984 DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " |
985 "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2, |
986 scr, sctlr, flags, tranType); 987 988 if ((req->isInstFetch() && (!sctlr.i)) || 989 ((!req->isInstFetch()) && (!sctlr.c))){ 990 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 991 } 992 if (!is_fetch) { 993 assert(flags & MustBeOne); --- 533 unchanged lines hidden --- |