1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 86 unchanged lines hidden (view full) --- 95void 96TLB::init() 97{ 98 if (stage2Mmu && !isStage2) 99 stage2Tlb = stage2Mmu->stage2Tlb(); 100} 101 102void |
103TLB::setMMU(Stage2MMU *m, MasterID master_id) |
104{ 105 stage2Mmu = m; |
106 tableWalker->setMMU(m, master_id); |
107} 108 109bool 110TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 111{ 112 updateMiscReg(tc); 113 114 if (directToStage2) { --- 1095 unchanged lines hidden (view full) --- 1210 translation->markDelayed(); 1211 } 1212 return fault; 1213} 1214 1215BaseMasterPort* 1216TLB::getMasterPort() 1217{ |
1218 return &stage2Mmu->getPort(); |
1219} 1220 |
1221void 1222TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) 1223{ 1224 // check if the regs have changed, or the translation mode is different. 1225 // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle 1226 // one type of translation anyway 1227 if (miscRegValid && ((tranType == curTranType) || isStage2)) { 1228 return; --- 216 unchanged lines hidden --- |