2c2
< * Copyright (c) 2010 ARM Limited
---
> * Copyright (c) 2010-2012 ARM Limited
255a256,263
> TLB::drainResume()
> {
> // We might have unserialized something or switched CPUs, so make
> // sure to re-read the misc regs.
> miscRegValid = false;
> }
>
> void
281d288
< miscRegValid = false;