68c68
< : BaseTLB(p), size(p->size), nlu(0)
---
> : BaseTLB(p), size(p->size)
71a72
> , rangeMRU(1)
101d101
< // XXX This should either turn into a TlbMap or add caching
105c105
< // Do some kind of caching, fast indexing, anything
---
> // Maitaining LRU array
110,112d109
< retval = &table[x];
< if (x == nlu && !functional)
< nextnlu();
113a111,120
> // We only move the hit entry ahead when the position is higher than rangeMRU
> if (x > rangeMRU) {
> TlbEntry tmp_entry = table[x];
> for(int i = x; i > 0; i--)
> table[i] = table[i-1];
> table[0] = tmp_entry;
> retval = &table[0];
> } else {
> retval = &table[x];
> }
137c144
< if (table[nlu].valid)
---
> if (table[size-1].valid)
139,140c146,148
< table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N,
< table[nlu].size, table[nlu].ap);
---
> table[size-1].vpn << table[size-1].N, table[size-1].asid,
> table[size-1].pfn << table[size-1].N, table[size-1].size,
> table[size-1].ap);
142,143c150
< // XXX Update caching, lookup table etc
< table[nlu] = entry;
---
> //inserting to MRU position and evicting the LRU one
145,146c152,154
< // XXX Figure out how entries are generally inserted in ARM
< nextnlu();
---
> for(int i = size-1; i > 0; i--)
> table[i] = table[i-1];
> table[0] = entry;
180d187
< nlu = 0;