814c814,826
< panic("Virtualization in AArch64 state is not supported yet");
---
> assert(ArmSystem::haveVirtualization(tc) && aarch64EL != EL2);
> // In stage 2 we use the hypervisor access permission bits.
> // The following permissions are described in ARM DDI 0487A.f
> // D4-1802
> uint8_t hap = 0x3 & te->hap;
> if (is_fetch) {
> // sctlr.wxn overrides the xn bit
> grant = !sctlr.wxn && !xn;
> } else if (is_write) {
> grant = hap & 0x2;
> } else { // is_read
> grant = hap & 0x1;
> }
1235a1248
> hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1238,1243c1251,1268
< // @todo: modify this behaviour to support Virtualization in
< // AArch64
< vmid = 0;
< isHyp = false;
< directToStage2 = false;
< stage2Req = false;
---
> if (haveVirtualization) {
> vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
> isHyp = tranType & HypMode;
> isHyp &= (tranType & S1S2NsTran) == 0;
> isHyp &= (tranType & S1CTran) == 0;
> // Work out if we should skip the first stage of translation and go
> // directly to stage 2. This value is cached so we don't have to
> // compute it for every translation.
> stage2Req = isStage2 ||
> (hcr.vm && !isHyp && !isSecure &&
> !(tranType & S1CTran) && (aarch64EL < EL2));
> directToStage2 = !isStage2 && stage2Req && !sctlr.m;
> } else {
> vmid = 0;
> isHyp = false;
> directToStage2 = false;
> stage2Req = false;
> }
1364a1390,1408
>
> if (isStage2) {
> // We are already in the stage 2 TLB. Grab the table entry for stage
> // 2 only. We are here because stage 1 translation is disabled.
> TlbEntry *s2Te = NULL;
> // Get the stage 2 table entry
> fault = getTE(&s2Te, req, tc, mode, translation, timing, functional,
> isSecure, curTranType);
> // Check permissions of stage 2
> if ((s2Te != NULL) && (fault = NoFault)) {
> if(aarch64)
> fault = checkPermissions64(s2Te, req, mode, tc);
> else
> fault = checkPermissions(s2Te, req, mode);
> }
> *te = s2Te;
> return fault;
> }
>