103c103
< TLB::setMMU(Stage2MMU *m)
---
> TLB::setMMU(Stage2MMU *m, MasterID master_id)
106c106
< tableWalker->setMMU(m);
---
> tableWalker->setMMU(m, master_id);
1218c1218
< return &tableWalker->getMasterPort("port");
---
> return &stage2Mmu->getPort();
1221,1226d1220
< DmaPort&
< TLB::getWalkerPort()
< {
< return tableWalker->getWalkerPort();
< }
<