97TlbEntry* 98TLB::lookup(Addr va, uint8_t cid, bool functional) 99{ 100 101 TlbEntry *retval = NULL; 102 103 // Maitaining LRU array 104 105 int x = 0; 106 while (retval == NULL && x < size) { 107 if (table[x].match(va, cid)) { 108 109 // We only move the hit entry ahead when the position is higher than rangeMRU 110 if (x > rangeMRU && !functional) { 111 TlbEntry tmp_entry = table[x]; 112 for(int i = x; i > 0; i--) 113 table[i] = table[i-1]; 114 table[0] = tmp_entry; 115 retval = &table[0]; 116 } else { 117 retval = &table[x]; 118 } 119 break; 120 } 121 x++; 122 } 123 124 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 125 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 126 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 127 retval ? retval->ap : 0); 128 ; 129 return retval; 130} 131 132// insert a new TLB entry 133void 134TLB::insert(Addr addr, TlbEntry &entry) 135{ 136 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 137 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 138 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 139 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 140 entry.xn, entry.ap, entry.domain); 141 142 if (table[size-1].valid) 143 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 144 table[size-1].vpn << table[size-1].N, table[size-1].asid, 145 table[size-1].pfn << table[size-1].N, table[size-1].size, 146 table[size-1].ap); 147 148 //inserting to MRU position and evicting the LRU one 149 150 for(int i = size-1; i > 0; i--) 151 table[i] = table[i-1]; 152 table[0] = entry; 153 154 inserts++; 155} 156 157void 158TLB::printTlb() 159{ 160 int x = 0; 161 TlbEntry *te; 162 DPRINTF(TLB, "Current TLB contents:\n"); 163 while (x < size) { 164 te = &table[x]; 165 if (te->valid) 166 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 167 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 168 x++; 169 } 170} 171 172 173void 174TLB::flushAll() 175{ 176 DPRINTF(TLB, "Flushing all TLB entries\n"); 177 int x = 0; 178 TlbEntry *te; 179 while (x < size) { 180 te = &table[x]; 181 if (te->valid) { 182 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 183 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 184 flushedEntries++; 185 } 186 x++; 187 } 188 189 memset(table, 0, sizeof(TlbEntry) * size); 190 191 flushTlb++; 192} 193 194 195void 196TLB::flushMvaAsid(Addr mva, uint64_t asn) 197{ 198 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 199 TlbEntry *te; 200 201 te = lookup(mva, asn); 202 while (te != NULL) { 203 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 204 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 205 te->valid = false; 206 flushedEntries++; 207 te = lookup(mva,asn); 208 } 209 flushTlbMvaAsid++; 210} 211 212void 213TLB::flushAsid(uint64_t asn) 214{ 215 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 216 217 int x = 0; 218 TlbEntry *te; 219 220 while (x < size) { 221 te = &table[x]; 222 if (te->asid == asn) { 223 te->valid = false; 224 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 225 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 226 flushedEntries++; 227 } 228 x++; 229 } 230 flushTlbAsid++; 231} 232 233void 234TLB::flushMva(Addr mva) 235{ 236 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 237 238 int x = 0; 239 TlbEntry *te; 240 241 while (x < size) { 242 te = &table[x]; 243 Addr v = te->vpn << te->N; 244 if (mva >= v && mva < v + te->size) { 245 te->valid = false; 246 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 247 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 248 flushedEntries++; 249 } 250 x++; 251 } 252 flushTlbMva++; 253} 254 255void 256TLB::drainResume() 257{ 258 // We might have unserialized something or switched CPUs, so make 259 // sure to re-read the misc regs. 260 miscRegValid = false; 261} 262 263void 264TLB::serialize(ostream &os) 265{ 266 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 267 268 SERIALIZE_SCALAR(_attr); 269 270 int num_entries = size; 271 SERIALIZE_SCALAR(num_entries); 272 for(int i = 0; i < size; i++){ 273 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 274 table[i].serialize(os); 275 } 276} 277 278void 279TLB::unserialize(Checkpoint *cp, const string §ion) 280{ 281 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 282 283 UNSERIALIZE_SCALAR(_attr); 284 int num_entries; 285 UNSERIALIZE_SCALAR(num_entries); 286 for(int i = 0; i < min(size, num_entries); i++){ 287 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 288 } 289} 290 291void 292TLB::regStats() 293{ 294 instHits 295 .name(name() + ".inst_hits") 296 .desc("ITB inst hits") 297 ; 298 299 instMisses 300 .name(name() + ".inst_misses") 301 .desc("ITB inst misses") 302 ; 303 304 instAccesses 305 .name(name() + ".inst_accesses") 306 .desc("ITB inst accesses") 307 ; 308 309 readHits 310 .name(name() + ".read_hits") 311 .desc("DTB read hits") 312 ; 313 314 readMisses 315 .name(name() + ".read_misses") 316 .desc("DTB read misses") 317 ; 318 319 readAccesses 320 .name(name() + ".read_accesses") 321 .desc("DTB read accesses") 322 ; 323 324 writeHits 325 .name(name() + ".write_hits") 326 .desc("DTB write hits") 327 ; 328 329 writeMisses 330 .name(name() + ".write_misses") 331 .desc("DTB write misses") 332 ; 333 334 writeAccesses 335 .name(name() + ".write_accesses") 336 .desc("DTB write accesses") 337 ; 338 339 hits 340 .name(name() + ".hits") 341 .desc("DTB hits") 342 ; 343 344 misses 345 .name(name() + ".misses") 346 .desc("DTB misses") 347 ; 348 349 accesses 350 .name(name() + ".accesses") 351 .desc("DTB accesses") 352 ; 353 354 flushTlb 355 .name(name() + ".flush_tlb") 356 .desc("Number of times complete TLB was flushed") 357 ; 358 359 flushTlbMva 360 .name(name() + ".flush_tlb_mva") 361 .desc("Number of times TLB was flushed by MVA") 362 ; 363 364 flushTlbMvaAsid 365 .name(name() + ".flush_tlb_mva_asid") 366 .desc("Number of times TLB was flushed by MVA & ASID") 367 ; 368 369 flushTlbAsid 370 .name(name() + ".flush_tlb_asid") 371 .desc("Number of times TLB was flushed by ASID") 372 ; 373 374 flushedEntries 375 .name(name() + ".flush_entries") 376 .desc("Number of entries that have been flushed from TLB") 377 ; 378 379 alignFaults 380 .name(name() + ".align_faults") 381 .desc("Number of TLB faults due to alignment restrictions") 382 ; 383 384 prefetchFaults 385 .name(name() + ".prefetch_faults") 386 .desc("Number of TLB faults due to prefetch") 387 ; 388 389 domainFaults 390 .name(name() + ".domain_faults") 391 .desc("Number of TLB faults due to domain restrictions") 392 ; 393 394 permsFaults 395 .name(name() + ".perms_faults") 396 .desc("Number of TLB faults due to permissions restrictions") 397 ; 398 399 instAccesses = instHits + instMisses; 400 readAccesses = readHits + readMisses; 401 writeAccesses = writeHits + writeMisses; 402 hits = readHits + writeHits + instHits; 403 misses = readMisses + writeMisses + instMisses; 404 accesses = readAccesses + writeAccesses + instAccesses; 405} 406 407Fault 408TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 409 Translation *translation, bool &delay, bool timing) 410{ 411 if (!miscRegValid) 412 updateMiscReg(tc); 413 Addr vaddr = req->getVaddr(); 414 uint32_t flags = req->getFlags(); 415 416 bool is_fetch = (mode == Execute); 417 bool is_write = (mode == Write); 418 419 if (!is_fetch) { 420 assert(flags & MustBeOne); 421 if (sctlr.a || !(flags & AllowUnaligned)) { 422 if (vaddr & flags & AlignmentMask) { 423 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 424 } 425 } 426 } 427 428 Addr paddr; 429 Process *p = tc->getProcessPtr(); 430 431 if (!p->pTable->translate(vaddr, paddr)) 432 return Fault(new GenericPageTableFault(vaddr)); 433 req->setPaddr(paddr); 434 435 return NoFault; 436} 437 438Fault 439TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 440{ 441 return NoFault; 442} 443 444Fault 445TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 446 bool is_write, uint8_t domain, bool sNp) 447{ 448 return NoFault; 449} 450 451Fault 452TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 453 Translation *translation, bool &delay, bool timing, bool functional) 454{ 455 // No such thing as a functional timing access 456 assert(!(timing && functional)); 457 458 if (!miscRegValid) { 459 updateMiscReg(tc); 460 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 461 } 462 463 Addr vaddr = req->getVaddr(); 464 uint32_t flags = req->getFlags(); 465 466 bool is_fetch = (mode == Execute); 467 bool is_write = (mode == Write); 468 bool is_priv = isPriv && !(flags & UserMode); 469 470 req->setAsid(contextId.asid); 471 472 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 473 isPriv, flags & UserMode); 474 // If this is a clrex instruction, provide a PA of 0 with no fault 475 // This will force the monitor to set the tracked address to 0 476 // a bit of a hack but this effectively clrears this processors monitor 477 if (flags & Request::CLEAR_LL){ 478 req->setPaddr(0); 479 req->setFlags(Request::UNCACHEABLE); 480 req->setFlags(Request::CLEAR_LL); 481 return NoFault; 482 } 483 if ((req->isInstFetch() && (!sctlr.i)) || 484 ((!req->isInstFetch()) && (!sctlr.c))){ 485 req->setFlags(Request::UNCACHEABLE); 486 } 487 if (!is_fetch) { 488 assert(flags & MustBeOne); 489 if (sctlr.a || !(flags & AllowUnaligned)) { 490 if (vaddr & flags & AlignmentMask) { 491 alignFaults++; 492 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 493 } 494 } 495 } 496 497 Fault fault; 498 499 if (!sctlr.m) { 500 req->setPaddr(vaddr); 501 if (sctlr.tre == 0) { 502 req->setFlags(Request::UNCACHEABLE); 503 } else { 504 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 505 req->setFlags(Request::UNCACHEABLE); 506 } 507 508 // Set memory attributes 509 TlbEntry temp_te; 510 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 511 temp_te.shareable = true; 512 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 513 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 514 temp_te.innerAttrs, temp_te.outerAttrs); 515 setAttr(temp_te.attributes); 516 517 return trickBoxCheck(req, mode, 0, false); 518 } 519 520 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 521 // Translation enabled 522 523 TlbEntry *te = lookup(vaddr, contextId); 524 if (te == NULL) { 525 if (req->isPrefetch()){ 526 //if the request is a prefetch don't attempt to fill the TLB 527 //or go any further with the memory access 528 prefetchFaults++; 529 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 530 } 531 532 if (is_fetch) 533 instMisses++; 534 else if (is_write) 535 writeMisses++; 536 else 537 readMisses++; 538 539 // start translation table walk, pass variables rather than 540 // re-retreaving in table walker for speed 541 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 542 vaddr, contextId); 543 fault = tableWalker->walk(req, tc, contextId, mode, translation, 544 timing, functional); 545 if (timing && fault == NoFault) { 546 delay = true; 547 // for timing mode, return and wait for table walk 548 return fault; 549 } 550 if (fault) 551 return fault; 552 553 te = lookup(vaddr, contextId); 554 if (!te) 555 printTlb(); 556 assert(te); 557 } else { 558 if (is_fetch) 559 instHits++; 560 else if (is_write) 561 writeHits++; 562 else 563 readHits++; 564 } 565 566 // Set memory attributes 567 DPRINTF(TLBVerbose, 568 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 569 outerAttrs: %d\n", 570 te->shareable, te->innerAttrs, te->outerAttrs); 571 setAttr(te->attributes); 572 if (te->nonCacheable) { 573 req->setFlags(Request::UNCACHEABLE); 574 575 // Prevent prefetching from I/O devices. 576 if (req->isPrefetch()) { 577 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 578 } 579 } 580 581 if (!bootUncacheability && 582 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) 583 req->setFlags(Request::UNCACHEABLE); 584 585 switch ( (dacr >> (te->domain * 2)) & 0x3) { 586 case 0: 587 domainFaults++; 588 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 589 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 590 if (is_fetch) 591 return new PrefetchAbort(vaddr, 592 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 593 else 594 return new DataAbort(vaddr, te->domain, is_write, 595 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 596 case 1: 597 // Continue with permissions check 598 break; 599 case 2: 600 panic("UNPRED domain\n"); 601 case 3: 602 req->setPaddr(te->pAddr(vaddr)); 603 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 604 if (fault) 605 return fault; 606 return NoFault; 607 } 608 609 uint8_t ap = te->ap; 610 611 if (sctlr.afe == 1) 612 ap |= 1; 613 614 bool abt; 615 616 /* if (!sctlr.xp) 617 ap &= 0x3; 618*/ 619 switch (ap) { 620 case 0: 621 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 622 if (!sctlr.xp) { 623 switch ((int)sctlr.rs) { 624 case 2: 625 abt = is_write; 626 break; 627 case 1: 628 abt = is_write || !is_priv; 629 break; 630 case 0: 631 case 3: 632 default: 633 abt = true; 634 break; 635 } 636 } else { 637 abt = true; 638 } 639 break; 640 case 1: 641 abt = !is_priv; 642 break; 643 case 2: 644 abt = !is_priv && is_write; 645 break; 646 case 3: 647 abt = false; 648 break; 649 case 4: 650 panic("UNPRED premissions\n"); 651 case 5: 652 abt = !is_priv || is_write; 653 break; 654 case 6: 655 case 7: 656 abt = is_write; 657 break; 658 default: 659 panic("Unknown permissions\n"); 660 } 661 if ((is_fetch) && (abt || te->xn)) { 662 permsFaults++; 663 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 664 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 665 return new PrefetchAbort(vaddr, 666 (te->sNp ? ArmFault::Permission0 : 667 ArmFault::Permission1)); 668 } else if (abt) { 669 permsFaults++; 670 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 671 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 672 return new DataAbort(vaddr, te->domain, is_write, 673 (te->sNp ? ArmFault::Permission0 : 674 ArmFault::Permission1)); 675 } 676 677 req->setPaddr(te->pAddr(vaddr)); 678 // Check for a trickbox generated address fault 679 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 680 if (fault) 681 return fault; 682 683 return NoFault; 684} 685 686Fault 687TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 688{ 689 bool delay = false; 690 Fault fault; 691 if (FullSystem) 692 fault = translateFs(req, tc, mode, NULL, delay, false); 693 else 694 fault = translateSe(req, tc, mode, NULL, delay, false); 695 assert(!delay); 696 return fault; 697} 698 699Fault 700TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 701{ 702 bool delay = false; 703 Fault fault; 704 if (FullSystem) 705 fault = translateFs(req, tc, mode, NULL, delay, false, true); 706 else 707 fault = translateSe(req, tc, mode, NULL, delay, false); 708 assert(!delay); 709 return fault; 710} 711 712Fault 713TLB::translateTiming(RequestPtr req, ThreadContext *tc, 714 Translation *translation, Mode mode) 715{ 716 assert(translation); 717 bool delay = false; 718 Fault fault; 719 if (FullSystem) 720 fault = translateFs(req, tc, mode, translation, delay, true); 721 else 722 fault = translateSe(req, tc, mode, translation, delay, true); 723 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 724 NoFault); 725 if (!delay) 726 translation->finish(fault, req, tc, mode); 727 else 728 translation->markDelayed(); 729 return fault; 730} 731 732BaseMasterPort* 733TLB::getMasterPort() 734{ 735 return &tableWalker->getMasterPort("port"); 736} 737 738 739 740ArmISA::TLB * 741ArmTLBParams::create() 742{ 743 return new ArmISA::TLB(this); 744}
| 103TlbEntry* 104TLB::lookup(Addr va, uint8_t cid, bool functional) 105{ 106 107 TlbEntry *retval = NULL; 108 109 // Maitaining LRU array 110 111 int x = 0; 112 while (retval == NULL && x < size) { 113 if (table[x].match(va, cid)) { 114 115 // We only move the hit entry ahead when the position is higher than rangeMRU 116 if (x > rangeMRU && !functional) { 117 TlbEntry tmp_entry = table[x]; 118 for(int i = x; i > 0; i--) 119 table[i] = table[i-1]; 120 table[0] = tmp_entry; 121 retval = &table[0]; 122 } else { 123 retval = &table[x]; 124 } 125 break; 126 } 127 x++; 128 } 129 130 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 131 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 132 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 133 retval ? retval->ap : 0); 134 ; 135 return retval; 136} 137 138// insert a new TLB entry 139void 140TLB::insert(Addr addr, TlbEntry &entry) 141{ 142 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 143 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 144 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 145 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 146 entry.xn, entry.ap, entry.domain); 147 148 if (table[size-1].valid) 149 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 150 table[size-1].vpn << table[size-1].N, table[size-1].asid, 151 table[size-1].pfn << table[size-1].N, table[size-1].size, 152 table[size-1].ap); 153 154 //inserting to MRU position and evicting the LRU one 155 156 for(int i = size-1; i > 0; i--) 157 table[i] = table[i-1]; 158 table[0] = entry; 159 160 inserts++; 161} 162 163void 164TLB::printTlb() 165{ 166 int x = 0; 167 TlbEntry *te; 168 DPRINTF(TLB, "Current TLB contents:\n"); 169 while (x < size) { 170 te = &table[x]; 171 if (te->valid) 172 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 173 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 174 x++; 175 } 176} 177 178 179void 180TLB::flushAll() 181{ 182 DPRINTF(TLB, "Flushing all TLB entries\n"); 183 int x = 0; 184 TlbEntry *te; 185 while (x < size) { 186 te = &table[x]; 187 if (te->valid) { 188 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 189 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 190 flushedEntries++; 191 } 192 x++; 193 } 194 195 memset(table, 0, sizeof(TlbEntry) * size); 196 197 flushTlb++; 198} 199 200 201void 202TLB::flushMvaAsid(Addr mva, uint64_t asn) 203{ 204 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 205 TlbEntry *te; 206 207 te = lookup(mva, asn); 208 while (te != NULL) { 209 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 210 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 211 te->valid = false; 212 flushedEntries++; 213 te = lookup(mva,asn); 214 } 215 flushTlbMvaAsid++; 216} 217 218void 219TLB::flushAsid(uint64_t asn) 220{ 221 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 222 223 int x = 0; 224 TlbEntry *te; 225 226 while (x < size) { 227 te = &table[x]; 228 if (te->asid == asn) { 229 te->valid = false; 230 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 231 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 232 flushedEntries++; 233 } 234 x++; 235 } 236 flushTlbAsid++; 237} 238 239void 240TLB::flushMva(Addr mva) 241{ 242 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 243 244 int x = 0; 245 TlbEntry *te; 246 247 while (x < size) { 248 te = &table[x]; 249 Addr v = te->vpn << te->N; 250 if (mva >= v && mva < v + te->size) { 251 te->valid = false; 252 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 253 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 254 flushedEntries++; 255 } 256 x++; 257 } 258 flushTlbMva++; 259} 260 261void 262TLB::drainResume() 263{ 264 // We might have unserialized something or switched CPUs, so make 265 // sure to re-read the misc regs. 266 miscRegValid = false; 267} 268 269void 270TLB::serialize(ostream &os) 271{ 272 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 273 274 SERIALIZE_SCALAR(_attr); 275 276 int num_entries = size; 277 SERIALIZE_SCALAR(num_entries); 278 for(int i = 0; i < size; i++){ 279 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 280 table[i].serialize(os); 281 } 282} 283 284void 285TLB::unserialize(Checkpoint *cp, const string §ion) 286{ 287 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 288 289 UNSERIALIZE_SCALAR(_attr); 290 int num_entries; 291 UNSERIALIZE_SCALAR(num_entries); 292 for(int i = 0; i < min(size, num_entries); i++){ 293 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 294 } 295} 296 297void 298TLB::regStats() 299{ 300 instHits 301 .name(name() + ".inst_hits") 302 .desc("ITB inst hits") 303 ; 304 305 instMisses 306 .name(name() + ".inst_misses") 307 .desc("ITB inst misses") 308 ; 309 310 instAccesses 311 .name(name() + ".inst_accesses") 312 .desc("ITB inst accesses") 313 ; 314 315 readHits 316 .name(name() + ".read_hits") 317 .desc("DTB read hits") 318 ; 319 320 readMisses 321 .name(name() + ".read_misses") 322 .desc("DTB read misses") 323 ; 324 325 readAccesses 326 .name(name() + ".read_accesses") 327 .desc("DTB read accesses") 328 ; 329 330 writeHits 331 .name(name() + ".write_hits") 332 .desc("DTB write hits") 333 ; 334 335 writeMisses 336 .name(name() + ".write_misses") 337 .desc("DTB write misses") 338 ; 339 340 writeAccesses 341 .name(name() + ".write_accesses") 342 .desc("DTB write accesses") 343 ; 344 345 hits 346 .name(name() + ".hits") 347 .desc("DTB hits") 348 ; 349 350 misses 351 .name(name() + ".misses") 352 .desc("DTB misses") 353 ; 354 355 accesses 356 .name(name() + ".accesses") 357 .desc("DTB accesses") 358 ; 359 360 flushTlb 361 .name(name() + ".flush_tlb") 362 .desc("Number of times complete TLB was flushed") 363 ; 364 365 flushTlbMva 366 .name(name() + ".flush_tlb_mva") 367 .desc("Number of times TLB was flushed by MVA") 368 ; 369 370 flushTlbMvaAsid 371 .name(name() + ".flush_tlb_mva_asid") 372 .desc("Number of times TLB was flushed by MVA & ASID") 373 ; 374 375 flushTlbAsid 376 .name(name() + ".flush_tlb_asid") 377 .desc("Number of times TLB was flushed by ASID") 378 ; 379 380 flushedEntries 381 .name(name() + ".flush_entries") 382 .desc("Number of entries that have been flushed from TLB") 383 ; 384 385 alignFaults 386 .name(name() + ".align_faults") 387 .desc("Number of TLB faults due to alignment restrictions") 388 ; 389 390 prefetchFaults 391 .name(name() + ".prefetch_faults") 392 .desc("Number of TLB faults due to prefetch") 393 ; 394 395 domainFaults 396 .name(name() + ".domain_faults") 397 .desc("Number of TLB faults due to domain restrictions") 398 ; 399 400 permsFaults 401 .name(name() + ".perms_faults") 402 .desc("Number of TLB faults due to permissions restrictions") 403 ; 404 405 instAccesses = instHits + instMisses; 406 readAccesses = readHits + readMisses; 407 writeAccesses = writeHits + writeMisses; 408 hits = readHits + writeHits + instHits; 409 misses = readMisses + writeMisses + instMisses; 410 accesses = readAccesses + writeAccesses + instAccesses; 411} 412 413Fault 414TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 415 Translation *translation, bool &delay, bool timing) 416{ 417 if (!miscRegValid) 418 updateMiscReg(tc); 419 Addr vaddr = req->getVaddr(); 420 uint32_t flags = req->getFlags(); 421 422 bool is_fetch = (mode == Execute); 423 bool is_write = (mode == Write); 424 425 if (!is_fetch) { 426 assert(flags & MustBeOne); 427 if (sctlr.a || !(flags & AllowUnaligned)) { 428 if (vaddr & flags & AlignmentMask) { 429 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 430 } 431 } 432 } 433 434 Addr paddr; 435 Process *p = tc->getProcessPtr(); 436 437 if (!p->pTable->translate(vaddr, paddr)) 438 return Fault(new GenericPageTableFault(vaddr)); 439 req->setPaddr(paddr); 440 441 return NoFault; 442} 443 444Fault 445TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 446{ 447 return NoFault; 448} 449 450Fault 451TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 452 bool is_write, uint8_t domain, bool sNp) 453{ 454 return NoFault; 455} 456 457Fault 458TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 459 Translation *translation, bool &delay, bool timing, bool functional) 460{ 461 // No such thing as a functional timing access 462 assert(!(timing && functional)); 463 464 if (!miscRegValid) { 465 updateMiscReg(tc); 466 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 467 } 468 469 Addr vaddr = req->getVaddr(); 470 uint32_t flags = req->getFlags(); 471 472 bool is_fetch = (mode == Execute); 473 bool is_write = (mode == Write); 474 bool is_priv = isPriv && !(flags & UserMode); 475 476 req->setAsid(contextId.asid); 477 478 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 479 isPriv, flags & UserMode); 480 // If this is a clrex instruction, provide a PA of 0 with no fault 481 // This will force the monitor to set the tracked address to 0 482 // a bit of a hack but this effectively clrears this processors monitor 483 if (flags & Request::CLEAR_LL){ 484 req->setPaddr(0); 485 req->setFlags(Request::UNCACHEABLE); 486 req->setFlags(Request::CLEAR_LL); 487 return NoFault; 488 } 489 if ((req->isInstFetch() && (!sctlr.i)) || 490 ((!req->isInstFetch()) && (!sctlr.c))){ 491 req->setFlags(Request::UNCACHEABLE); 492 } 493 if (!is_fetch) { 494 assert(flags & MustBeOne); 495 if (sctlr.a || !(flags & AllowUnaligned)) { 496 if (vaddr & flags & AlignmentMask) { 497 alignFaults++; 498 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 499 } 500 } 501 } 502 503 Fault fault; 504 505 if (!sctlr.m) { 506 req->setPaddr(vaddr); 507 if (sctlr.tre == 0) { 508 req->setFlags(Request::UNCACHEABLE); 509 } else { 510 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 511 req->setFlags(Request::UNCACHEABLE); 512 } 513 514 // Set memory attributes 515 TlbEntry temp_te; 516 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 517 temp_te.shareable = true; 518 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 519 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 520 temp_te.innerAttrs, temp_te.outerAttrs); 521 setAttr(temp_te.attributes); 522 523 return trickBoxCheck(req, mode, 0, false); 524 } 525 526 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 527 // Translation enabled 528 529 TlbEntry *te = lookup(vaddr, contextId); 530 if (te == NULL) { 531 if (req->isPrefetch()){ 532 //if the request is a prefetch don't attempt to fill the TLB 533 //or go any further with the memory access 534 prefetchFaults++; 535 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 536 } 537 538 if (is_fetch) 539 instMisses++; 540 else if (is_write) 541 writeMisses++; 542 else 543 readMisses++; 544 545 // start translation table walk, pass variables rather than 546 // re-retreaving in table walker for speed 547 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 548 vaddr, contextId); 549 fault = tableWalker->walk(req, tc, contextId, mode, translation, 550 timing, functional); 551 if (timing && fault == NoFault) { 552 delay = true; 553 // for timing mode, return and wait for table walk 554 return fault; 555 } 556 if (fault) 557 return fault; 558 559 te = lookup(vaddr, contextId); 560 if (!te) 561 printTlb(); 562 assert(te); 563 } else { 564 if (is_fetch) 565 instHits++; 566 else if (is_write) 567 writeHits++; 568 else 569 readHits++; 570 } 571 572 // Set memory attributes 573 DPRINTF(TLBVerbose, 574 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 575 outerAttrs: %d\n", 576 te->shareable, te->innerAttrs, te->outerAttrs); 577 setAttr(te->attributes); 578 if (te->nonCacheable) { 579 req->setFlags(Request::UNCACHEABLE); 580 581 // Prevent prefetching from I/O devices. 582 if (req->isPrefetch()) { 583 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 584 } 585 } 586 587 if (!bootUncacheability && 588 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) 589 req->setFlags(Request::UNCACHEABLE); 590 591 switch ( (dacr >> (te->domain * 2)) & 0x3) { 592 case 0: 593 domainFaults++; 594 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 595 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 596 if (is_fetch) 597 return new PrefetchAbort(vaddr, 598 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 599 else 600 return new DataAbort(vaddr, te->domain, is_write, 601 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 602 case 1: 603 // Continue with permissions check 604 break; 605 case 2: 606 panic("UNPRED domain\n"); 607 case 3: 608 req->setPaddr(te->pAddr(vaddr)); 609 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 610 if (fault) 611 return fault; 612 return NoFault; 613 } 614 615 uint8_t ap = te->ap; 616 617 if (sctlr.afe == 1) 618 ap |= 1; 619 620 bool abt; 621 622 /* if (!sctlr.xp) 623 ap &= 0x3; 624*/ 625 switch (ap) { 626 case 0: 627 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 628 if (!sctlr.xp) { 629 switch ((int)sctlr.rs) { 630 case 2: 631 abt = is_write; 632 break; 633 case 1: 634 abt = is_write || !is_priv; 635 break; 636 case 0: 637 case 3: 638 default: 639 abt = true; 640 break; 641 } 642 } else { 643 abt = true; 644 } 645 break; 646 case 1: 647 abt = !is_priv; 648 break; 649 case 2: 650 abt = !is_priv && is_write; 651 break; 652 case 3: 653 abt = false; 654 break; 655 case 4: 656 panic("UNPRED premissions\n"); 657 case 5: 658 abt = !is_priv || is_write; 659 break; 660 case 6: 661 case 7: 662 abt = is_write; 663 break; 664 default: 665 panic("Unknown permissions\n"); 666 } 667 if ((is_fetch) && (abt || te->xn)) { 668 permsFaults++; 669 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 670 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 671 return new PrefetchAbort(vaddr, 672 (te->sNp ? ArmFault::Permission0 : 673 ArmFault::Permission1)); 674 } else if (abt) { 675 permsFaults++; 676 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 677 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 678 return new DataAbort(vaddr, te->domain, is_write, 679 (te->sNp ? ArmFault::Permission0 : 680 ArmFault::Permission1)); 681 } 682 683 req->setPaddr(te->pAddr(vaddr)); 684 // Check for a trickbox generated address fault 685 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 686 if (fault) 687 return fault; 688 689 return NoFault; 690} 691 692Fault 693TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 694{ 695 bool delay = false; 696 Fault fault; 697 if (FullSystem) 698 fault = translateFs(req, tc, mode, NULL, delay, false); 699 else 700 fault = translateSe(req, tc, mode, NULL, delay, false); 701 assert(!delay); 702 return fault; 703} 704 705Fault 706TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 707{ 708 bool delay = false; 709 Fault fault; 710 if (FullSystem) 711 fault = translateFs(req, tc, mode, NULL, delay, false, true); 712 else 713 fault = translateSe(req, tc, mode, NULL, delay, false); 714 assert(!delay); 715 return fault; 716} 717 718Fault 719TLB::translateTiming(RequestPtr req, ThreadContext *tc, 720 Translation *translation, Mode mode) 721{ 722 assert(translation); 723 bool delay = false; 724 Fault fault; 725 if (FullSystem) 726 fault = translateFs(req, tc, mode, translation, delay, true); 727 else 728 fault = translateSe(req, tc, mode, translation, delay, true); 729 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 730 NoFault); 731 if (!delay) 732 translation->finish(fault, req, tc, mode); 733 else 734 translation->markDelayed(); 735 return fault; 736} 737 738BaseMasterPort* 739TLB::getMasterPort() 740{ 741 return &tableWalker->getMasterPort("port"); 742} 743 744 745 746ArmISA::TLB * 747ArmTLBParams::create() 748{ 749 return new ArmISA::TLB(this); 750}
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