1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
|
| 50#include "arch/arm/table_walker.hh"
|
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Checkpoint.hh"
57#include "debug/TLB.hh"
58#include "debug/TLBVerbose.hh"
59#include "mem/page_table.hh"
60#include "params/ArmTLB.hh"
| 51#include "arch/arm/tlb.hh"
52#include "arch/arm/utility.hh"
53#include "base/inifile.hh"
54#include "base/str.hh"
55#include "base/trace.hh"
56#include "cpu/thread_context.hh"
57#include "debug/Checkpoint.hh"
58#include "debug/TLB.hh"
59#include "debug/TLBVerbose.hh"
60#include "mem/page_table.hh"
61#include "params/ArmTLB.hh"
|
| 62#include "sim/full_system.hh"
|
61#include "sim/process.hh"
62
63#if FULL_SYSTEM
64#include "arch/arm/system.hh"
| 63#include "sim/process.hh"
64
65#if FULL_SYSTEM
66#include "arch/arm/system.hh"
|
65#include "arch/arm/table_walker.hh"
| |
66#endif
67
68using namespace std;
69using namespace ArmISA;
70
71TLB::TLB(const Params *p)
| 67#endif
68
69using namespace std;
70using namespace ArmISA;
71
72TLB::TLB(const Params *p)
|
72 : BaseTLB(p), size(p->size)
73#if FULL_SYSTEM
74 , tableWalker(p->walker)
75#endif
76 , rangeMRU(1), bootUncacheability(false), miscRegValid(false)
| 73 : BaseTLB(p), size(p->size) , tableWalker(p->walker),
74 rangeMRU(1), bootUncacheability(false), miscRegValid(false)
|
77{
78 table = new TlbEntry[size];
79 memset(table, 0, sizeof(TlbEntry) * size);
80
| 75{
76 table = new TlbEntry[size];
77 memset(table, 0, sizeof(TlbEntry) * size);
78
|
81#if FULL_SYSTEM
| |
82 tableWalker->setTlb(this);
| 79 tableWalker->setTlb(this);
|
83#endif
| |
84}
85
86TLB::~TLB()
87{
88 if (table)
89 delete [] table;
90}
91
92bool
93TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
94{
95 if (!miscRegValid)
96 updateMiscReg(tc);
97 TlbEntry *e = lookup(va, contextId, true);
98 if (!e)
99 return false;
100 pa = e->pAddr(va);
101 return true;
102}
103
104TlbEntry*
105TLB::lookup(Addr va, uint8_t cid, bool functional)
106{
107
108 TlbEntry *retval = NULL;
109
110 // Maitaining LRU array
111
112 int x = 0;
113 while (retval == NULL && x < size) {
114 if (table[x].match(va, cid)) {
115
116 // We only move the hit entry ahead when the position is higher than rangeMRU
117 if (x > rangeMRU) {
118 TlbEntry tmp_entry = table[x];
119 for(int i = x; i > 0; i--)
120 table[i] = table[i-1];
121 table[0] = tmp_entry;
122 retval = &table[0];
123 } else {
124 retval = &table[x];
125 }
126 break;
127 }
128 x++;
129 }
130
131 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
132 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
133 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
134 retval ? retval->ap : 0);
135 ;
136 return retval;
137}
138
139// insert a new TLB entry
140void
141TLB::insert(Addr addr, TlbEntry &entry)
142{
143 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
144 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
145 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
146 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
147 entry.xn, entry.ap, entry.domain);
148
149 if (table[size-1].valid)
150 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
151 table[size-1].vpn << table[size-1].N, table[size-1].asid,
152 table[size-1].pfn << table[size-1].N, table[size-1].size,
153 table[size-1].ap);
154
155 //inserting to MRU position and evicting the LRU one
156
157 for(int i = size-1; i > 0; i--)
158 table[i] = table[i-1];
159 table[0] = entry;
160
161 inserts++;
162}
163
164void
165TLB::printTlb()
166{
167 int x = 0;
168 TlbEntry *te;
169 DPRINTF(TLB, "Current TLB contents:\n");
170 while (x < size) {
171 te = &table[x];
172 if (te->valid)
173 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
174 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
175 x++;
176 }
177}
178
179
180void
181TLB::flushAll()
182{
183 DPRINTF(TLB, "Flushing all TLB entries\n");
184 int x = 0;
185 TlbEntry *te;
186 while (x < size) {
187 te = &table[x];
188 if (te->valid) {
189 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
190 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
191 flushedEntries++;
192 }
193 x++;
194 }
195
196 memset(table, 0, sizeof(TlbEntry) * size);
197
198 flushTlb++;
199}
200
201
202void
203TLB::flushMvaAsid(Addr mva, uint64_t asn)
204{
205 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
206 TlbEntry *te;
207
208 te = lookup(mva, asn);
209 while (te != NULL) {
210 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
211 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
212 te->valid = false;
213 flushedEntries++;
214 te = lookup(mva,asn);
215 }
216 flushTlbMvaAsid++;
217}
218
219void
220TLB::flushAsid(uint64_t asn)
221{
222 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
223
224 int x = 0;
225 TlbEntry *te;
226
227 while (x < size) {
228 te = &table[x];
229 if (te->asid == asn) {
230 te->valid = false;
231 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
232 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
233 flushedEntries++;
234 }
235 x++;
236 }
237 flushTlbAsid++;
238}
239
240void
241TLB::flushMva(Addr mva)
242{
243 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
244
245 int x = 0;
246 TlbEntry *te;
247
248 while (x < size) {
249 te = &table[x];
250 Addr v = te->vpn << te->N;
251 if (mva >= v && mva < v + te->size) {
252 te->valid = false;
253 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
254 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
255 flushedEntries++;
256 }
257 x++;
258 }
259 flushTlbMva++;
260}
261
262void
263TLB::serialize(ostream &os)
264{
265 DPRINTF(Checkpoint, "Serializing Arm TLB\n");
266
267 SERIALIZE_SCALAR(_attr);
268
269 int num_entries = size;
270 SERIALIZE_SCALAR(num_entries);
271 for(int i = 0; i < size; i++){
272 nameOut(os, csprintf("%s.TlbEntry%d", name(), i));
273 table[i].serialize(os);
274 }
275}
276
277void
278TLB::unserialize(Checkpoint *cp, const string §ion)
279{
280 DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
281
282 UNSERIALIZE_SCALAR(_attr);
283 int num_entries;
284 UNSERIALIZE_SCALAR(num_entries);
285 for(int i = 0; i < min(size, num_entries); i++){
286 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
287 }
288 miscRegValid = false;
289}
290
291void
292TLB::regStats()
293{
294 instHits
295 .name(name() + ".inst_hits")
296 .desc("ITB inst hits")
297 ;
298
299 instMisses
300 .name(name() + ".inst_misses")
301 .desc("ITB inst misses")
302 ;
303
304 instAccesses
305 .name(name() + ".inst_accesses")
306 .desc("ITB inst accesses")
307 ;
308
309 readHits
310 .name(name() + ".read_hits")
311 .desc("DTB read hits")
312 ;
313
314 readMisses
315 .name(name() + ".read_misses")
316 .desc("DTB read misses")
317 ;
318
319 readAccesses
320 .name(name() + ".read_accesses")
321 .desc("DTB read accesses")
322 ;
323
324 writeHits
325 .name(name() + ".write_hits")
326 .desc("DTB write hits")
327 ;
328
329 writeMisses
330 .name(name() + ".write_misses")
331 .desc("DTB write misses")
332 ;
333
334 writeAccesses
335 .name(name() + ".write_accesses")
336 .desc("DTB write accesses")
337 ;
338
339 hits
340 .name(name() + ".hits")
341 .desc("DTB hits")
342 ;
343
344 misses
345 .name(name() + ".misses")
346 .desc("DTB misses")
347 ;
348
349 accesses
350 .name(name() + ".accesses")
351 .desc("DTB accesses")
352 ;
353
354 flushTlb
355 .name(name() + ".flush_tlb")
356 .desc("Number of times complete TLB was flushed")
357 ;
358
359 flushTlbMva
360 .name(name() + ".flush_tlb_mva")
361 .desc("Number of times TLB was flushed by MVA")
362 ;
363
364 flushTlbMvaAsid
365 .name(name() + ".flush_tlb_mva_asid")
366 .desc("Number of times TLB was flushed by MVA & ASID")
367 ;
368
369 flushTlbAsid
370 .name(name() + ".flush_tlb_asid")
371 .desc("Number of times TLB was flushed by ASID")
372 ;
373
374 flushedEntries
375 .name(name() + ".flush_entries")
376 .desc("Number of entries that have been flushed from TLB")
377 ;
378
379 alignFaults
380 .name(name() + ".align_faults")
381 .desc("Number of TLB faults due to alignment restrictions")
382 ;
383
384 prefetchFaults
385 .name(name() + ".prefetch_faults")
386 .desc("Number of TLB faults due to prefetch")
387 ;
388
389 domainFaults
390 .name(name() + ".domain_faults")
391 .desc("Number of TLB faults due to domain restrictions")
392 ;
393
394 permsFaults
395 .name(name() + ".perms_faults")
396 .desc("Number of TLB faults due to permissions restrictions")
397 ;
398
399 instAccesses = instHits + instMisses;
400 readAccesses = readHits + readMisses;
401 writeAccesses = writeHits + writeMisses;
402 hits = readHits + writeHits + instHits;
403 misses = readMisses + writeMisses + instMisses;
404 accesses = readAccesses + writeAccesses + instAccesses;
405}
406
| 80}
81
82TLB::~TLB()
83{
84 if (table)
85 delete [] table;
86}
87
88bool
89TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
90{
91 if (!miscRegValid)
92 updateMiscReg(tc);
93 TlbEntry *e = lookup(va, contextId, true);
94 if (!e)
95 return false;
96 pa = e->pAddr(va);
97 return true;
98}
99
100TlbEntry*
101TLB::lookup(Addr va, uint8_t cid, bool functional)
102{
103
104 TlbEntry *retval = NULL;
105
106 // Maitaining LRU array
107
108 int x = 0;
109 while (retval == NULL && x < size) {
110 if (table[x].match(va, cid)) {
111
112 // We only move the hit entry ahead when the position is higher than rangeMRU
113 if (x > rangeMRU) {
114 TlbEntry tmp_entry = table[x];
115 for(int i = x; i > 0; i--)
116 table[i] = table[i-1];
117 table[0] = tmp_entry;
118 retval = &table[0];
119 } else {
120 retval = &table[x];
121 }
122 break;
123 }
124 x++;
125 }
126
127 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
128 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
129 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
130 retval ? retval->ap : 0);
131 ;
132 return retval;
133}
134
135// insert a new TLB entry
136void
137TLB::insert(Addr addr, TlbEntry &entry)
138{
139 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
140 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
141 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
142 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
143 entry.xn, entry.ap, entry.domain);
144
145 if (table[size-1].valid)
146 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
147 table[size-1].vpn << table[size-1].N, table[size-1].asid,
148 table[size-1].pfn << table[size-1].N, table[size-1].size,
149 table[size-1].ap);
150
151 //inserting to MRU position and evicting the LRU one
152
153 for(int i = size-1; i > 0; i--)
154 table[i] = table[i-1];
155 table[0] = entry;
156
157 inserts++;
158}
159
160void
161TLB::printTlb()
162{
163 int x = 0;
164 TlbEntry *te;
165 DPRINTF(TLB, "Current TLB contents:\n");
166 while (x < size) {
167 te = &table[x];
168 if (te->valid)
169 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
170 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
171 x++;
172 }
173}
174
175
176void
177TLB::flushAll()
178{
179 DPRINTF(TLB, "Flushing all TLB entries\n");
180 int x = 0;
181 TlbEntry *te;
182 while (x < size) {
183 te = &table[x];
184 if (te->valid) {
185 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
186 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
187 flushedEntries++;
188 }
189 x++;
190 }
191
192 memset(table, 0, sizeof(TlbEntry) * size);
193
194 flushTlb++;
195}
196
197
198void
199TLB::flushMvaAsid(Addr mva, uint64_t asn)
200{
201 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
202 TlbEntry *te;
203
204 te = lookup(mva, asn);
205 while (te != NULL) {
206 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
207 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
208 te->valid = false;
209 flushedEntries++;
210 te = lookup(mva,asn);
211 }
212 flushTlbMvaAsid++;
213}
214
215void
216TLB::flushAsid(uint64_t asn)
217{
218 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
219
220 int x = 0;
221 TlbEntry *te;
222
223 while (x < size) {
224 te = &table[x];
225 if (te->asid == asn) {
226 te->valid = false;
227 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
228 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
229 flushedEntries++;
230 }
231 x++;
232 }
233 flushTlbAsid++;
234}
235
236void
237TLB::flushMva(Addr mva)
238{
239 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
240
241 int x = 0;
242 TlbEntry *te;
243
244 while (x < size) {
245 te = &table[x];
246 Addr v = te->vpn << te->N;
247 if (mva >= v && mva < v + te->size) {
248 te->valid = false;
249 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
250 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
251 flushedEntries++;
252 }
253 x++;
254 }
255 flushTlbMva++;
256}
257
258void
259TLB::serialize(ostream &os)
260{
261 DPRINTF(Checkpoint, "Serializing Arm TLB\n");
262
263 SERIALIZE_SCALAR(_attr);
264
265 int num_entries = size;
266 SERIALIZE_SCALAR(num_entries);
267 for(int i = 0; i < size; i++){
268 nameOut(os, csprintf("%s.TlbEntry%d", name(), i));
269 table[i].serialize(os);
270 }
271}
272
273void
274TLB::unserialize(Checkpoint *cp, const string §ion)
275{
276 DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
277
278 UNSERIALIZE_SCALAR(_attr);
279 int num_entries;
280 UNSERIALIZE_SCALAR(num_entries);
281 for(int i = 0; i < min(size, num_entries); i++){
282 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
283 }
284 miscRegValid = false;
285}
286
287void
288TLB::regStats()
289{
290 instHits
291 .name(name() + ".inst_hits")
292 .desc("ITB inst hits")
293 ;
294
295 instMisses
296 .name(name() + ".inst_misses")
297 .desc("ITB inst misses")
298 ;
299
300 instAccesses
301 .name(name() + ".inst_accesses")
302 .desc("ITB inst accesses")
303 ;
304
305 readHits
306 .name(name() + ".read_hits")
307 .desc("DTB read hits")
308 ;
309
310 readMisses
311 .name(name() + ".read_misses")
312 .desc("DTB read misses")
313 ;
314
315 readAccesses
316 .name(name() + ".read_accesses")
317 .desc("DTB read accesses")
318 ;
319
320 writeHits
321 .name(name() + ".write_hits")
322 .desc("DTB write hits")
323 ;
324
325 writeMisses
326 .name(name() + ".write_misses")
327 .desc("DTB write misses")
328 ;
329
330 writeAccesses
331 .name(name() + ".write_accesses")
332 .desc("DTB write accesses")
333 ;
334
335 hits
336 .name(name() + ".hits")
337 .desc("DTB hits")
338 ;
339
340 misses
341 .name(name() + ".misses")
342 .desc("DTB misses")
343 ;
344
345 accesses
346 .name(name() + ".accesses")
347 .desc("DTB accesses")
348 ;
349
350 flushTlb
351 .name(name() + ".flush_tlb")
352 .desc("Number of times complete TLB was flushed")
353 ;
354
355 flushTlbMva
356 .name(name() + ".flush_tlb_mva")
357 .desc("Number of times TLB was flushed by MVA")
358 ;
359
360 flushTlbMvaAsid
361 .name(name() + ".flush_tlb_mva_asid")
362 .desc("Number of times TLB was flushed by MVA & ASID")
363 ;
364
365 flushTlbAsid
366 .name(name() + ".flush_tlb_asid")
367 .desc("Number of times TLB was flushed by ASID")
368 ;
369
370 flushedEntries
371 .name(name() + ".flush_entries")
372 .desc("Number of entries that have been flushed from TLB")
373 ;
374
375 alignFaults
376 .name(name() + ".align_faults")
377 .desc("Number of TLB faults due to alignment restrictions")
378 ;
379
380 prefetchFaults
381 .name(name() + ".prefetch_faults")
382 .desc("Number of TLB faults due to prefetch")
383 ;
384
385 domainFaults
386 .name(name() + ".domain_faults")
387 .desc("Number of TLB faults due to domain restrictions")
388 ;
389
390 permsFaults
391 .name(name() + ".perms_faults")
392 .desc("Number of TLB faults due to permissions restrictions")
393 ;
394
395 instAccesses = instHits + instMisses;
396 readAccesses = readHits + readMisses;
397 writeAccesses = writeHits + writeMisses;
398 hits = readHits + writeHits + instHits;
399 misses = readMisses + writeMisses + instMisses;
400 accesses = readAccesses + writeAccesses + instAccesses;
401}
402
|
407#if !FULL_SYSTEM
| |
408Fault
409TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
410 Translation *translation, bool &delay, bool timing)
411{
412 if (!miscRegValid)
413 updateMiscReg(tc);
414 Addr vaddr = req->getVaddr();
415 uint32_t flags = req->getFlags();
416
417 bool is_fetch = (mode == Execute);
418 bool is_write = (mode == Write);
419
420 if (!is_fetch) {
421 assert(flags & MustBeOne);
422 if (sctlr.a || !(flags & AllowUnaligned)) {
423 if (vaddr & flags & AlignmentMask) {
424 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
425 }
426 }
427 }
428
| 403Fault
404TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
405 Translation *translation, bool &delay, bool timing)
406{
407 if (!miscRegValid)
408 updateMiscReg(tc);
409 Addr vaddr = req->getVaddr();
410 uint32_t flags = req->getFlags();
411
412 bool is_fetch = (mode == Execute);
413 bool is_write = (mode == Write);
414
415 if (!is_fetch) {
416 assert(flags & MustBeOne);
417 if (sctlr.a || !(flags & AllowUnaligned)) {
418 if (vaddr & flags & AlignmentMask) {
419 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
420 }
421 }
422 }
423
|
| 424#if !FULL_SYSTEM
|
429 Addr paddr;
430 Process *p = tc->getProcessPtr();
431
432 if (!p->pTable->translate(vaddr, paddr))
433 return Fault(new GenericPageTableFault(vaddr));
434 req->setPaddr(paddr);
| 425 Addr paddr;
426 Process *p = tc->getProcessPtr();
427
428 if (!p->pTable->translate(vaddr, paddr))
429 return Fault(new GenericPageTableFault(vaddr));
430 req->setPaddr(paddr);
|
| 431#endif
|
435
436 return NoFault;
437}
438
| 432
433 return NoFault;
434}
435
|
439#else // FULL_SYSTEM
440
| |
441Fault
442TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
443{
444 return NoFault;
445}
446
447Fault
448TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
449 bool is_write, uint8_t domain, bool sNp)
450{
451 return NoFault;
452}
453
454Fault
455TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
| 436Fault
437TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
438{
439 return NoFault;
440}
441
442Fault
443TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
444 bool is_write, uint8_t domain, bool sNp)
445{
446 return NoFault;
447}
448
449Fault
450TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
|
456 Translation *translation, bool &delay, bool timing, bool functional)
| 451 Translation *translation, bool &delay, bool timing)
|
457{
| 452{
|
458 // No such thing as a functional timing access
459 assert(!(timing && functional));
460
| |
461 if (!miscRegValid) {
462 updateMiscReg(tc);
463 DPRINTF(TLBVerbose, "TLB variables changed!\n");
464 }
465
466 Addr vaddr = req->getVaddr();
467 uint32_t flags = req->getFlags();
468
469 bool is_fetch = (mode == Execute);
470 bool is_write = (mode == Write);
471 bool is_priv = isPriv && !(flags & UserMode);
472
473 req->setAsid(contextId.asid);
474
475 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
476 isPriv, flags & UserMode);
477 // If this is a clrex instruction, provide a PA of 0 with no fault
478 // This will force the monitor to set the tracked address to 0
479 // a bit of a hack but this effectively clrears this processors monitor
480 if (flags & Request::CLEAR_LL){
481 req->setPaddr(0);
482 req->setFlags(Request::UNCACHEABLE);
483 req->setFlags(Request::CLEAR_LL);
484 return NoFault;
485 }
486 if ((req->isInstFetch() && (!sctlr.i)) ||
487 ((!req->isInstFetch()) && (!sctlr.c))){
488 req->setFlags(Request::UNCACHEABLE);
489 }
490 if (!is_fetch) {
491 assert(flags & MustBeOne);
492 if (sctlr.a || !(flags & AllowUnaligned)) {
493 if (vaddr & flags & AlignmentMask) {
494 alignFaults++;
495 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
496 }
497 }
498 }
499
500 Fault fault;
501
502 if (!sctlr.m) {
503 req->setPaddr(vaddr);
504 if (sctlr.tre == 0) {
505 req->setFlags(Request::UNCACHEABLE);
506 } else {
507 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
508 req->setFlags(Request::UNCACHEABLE);
509 }
510
511 // Set memory attributes
512 TlbEntry temp_te;
513 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
514 temp_te.shareable = true;
515 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
516 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
517 temp_te.innerAttrs, temp_te.outerAttrs);
518 setAttr(temp_te.attributes);
519
520 return trickBoxCheck(req, mode, 0, false);
521 }
522
523 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId);
524 // Translation enabled
525
526 TlbEntry *te = lookup(vaddr, contextId);
527 if (te == NULL) {
528 if (req->isPrefetch()){
529 //if the request is a prefetch don't attempt to fill the TLB
530 //or go any further with the memory access
531 prefetchFaults++;
532 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
533 }
534
535 if (is_fetch)
536 instMisses++;
537 else if (is_write)
538 writeMisses++;
539 else
540 readMisses++;
541
542 // start translation table walk, pass variables rather than
543 // re-retreaving in table walker for speed
544 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
545 vaddr, contextId);
546 fault = tableWalker->walk(req, tc, contextId, mode, translation,
| 453 if (!miscRegValid) {
454 updateMiscReg(tc);
455 DPRINTF(TLBVerbose, "TLB variables changed!\n");
456 }
457
458 Addr vaddr = req->getVaddr();
459 uint32_t flags = req->getFlags();
460
461 bool is_fetch = (mode == Execute);
462 bool is_write = (mode == Write);
463 bool is_priv = isPriv && !(flags & UserMode);
464
465 req->setAsid(contextId.asid);
466
467 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
468 isPriv, flags & UserMode);
469 // If this is a clrex instruction, provide a PA of 0 with no fault
470 // This will force the monitor to set the tracked address to 0
471 // a bit of a hack but this effectively clrears this processors monitor
472 if (flags & Request::CLEAR_LL){
473 req->setPaddr(0);
474 req->setFlags(Request::UNCACHEABLE);
475 req->setFlags(Request::CLEAR_LL);
476 return NoFault;
477 }
478 if ((req->isInstFetch() && (!sctlr.i)) ||
479 ((!req->isInstFetch()) && (!sctlr.c))){
480 req->setFlags(Request::UNCACHEABLE);
481 }
482 if (!is_fetch) {
483 assert(flags & MustBeOne);
484 if (sctlr.a || !(flags & AllowUnaligned)) {
485 if (vaddr & flags & AlignmentMask) {
486 alignFaults++;
487 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
488 }
489 }
490 }
491
492 Fault fault;
493
494 if (!sctlr.m) {
495 req->setPaddr(vaddr);
496 if (sctlr.tre == 0) {
497 req->setFlags(Request::UNCACHEABLE);
498 } else {
499 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
500 req->setFlags(Request::UNCACHEABLE);
501 }
502
503 // Set memory attributes
504 TlbEntry temp_te;
505 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
506 temp_te.shareable = true;
507 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
508 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
509 temp_te.innerAttrs, temp_te.outerAttrs);
510 setAttr(temp_te.attributes);
511
512 return trickBoxCheck(req, mode, 0, false);
513 }
514
515 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId);
516 // Translation enabled
517
518 TlbEntry *te = lookup(vaddr, contextId);
519 if (te == NULL) {
520 if (req->isPrefetch()){
521 //if the request is a prefetch don't attempt to fill the TLB
522 //or go any further with the memory access
523 prefetchFaults++;
524 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
525 }
526
527 if (is_fetch)
528 instMisses++;
529 else if (is_write)
530 writeMisses++;
531 else
532 readMisses++;
533
534 // start translation table walk, pass variables rather than
535 // re-retreaving in table walker for speed
536 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
537 vaddr, contextId);
538 fault = tableWalker->walk(req, tc, contextId, mode, translation,
|
547 timing, functional);
| 539 timing);
|
548 if (timing && fault == NoFault) {
549 delay = true;
550 // for timing mode, return and wait for table walk
551 return fault;
552 }
553 if (fault)
554 return fault;
555
556 te = lookup(vaddr, contextId);
557 if (!te)
558 printTlb();
559 assert(te);
560 } else {
561 if (is_fetch)
562 instHits++;
563 else if (is_write)
564 writeHits++;
565 else
566 readHits++;
567 }
568
569 // Set memory attributes
570 DPRINTF(TLBVerbose,
571 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
572 outerAttrs: %d\n",
573 te->shareable, te->innerAttrs, te->outerAttrs);
574 setAttr(te->attributes);
575 if (te->nonCacheable) {
576 req->setFlags(Request::UNCACHEABLE);
577
578 // Prevent prefetching from I/O devices.
579 if (req->isPrefetch()) {
580 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
581 }
582 }
583
| 540 if (timing && fault == NoFault) {
541 delay = true;
542 // for timing mode, return and wait for table walk
543 return fault;
544 }
545 if (fault)
546 return fault;
547
548 te = lookup(vaddr, contextId);
549 if (!te)
550 printTlb();
551 assert(te);
552 } else {
553 if (is_fetch)
554 instHits++;
555 else if (is_write)
556 writeHits++;
557 else
558 readHits++;
559 }
560
561 // Set memory attributes
562 DPRINTF(TLBVerbose,
563 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
564 outerAttrs: %d\n",
565 te->shareable, te->innerAttrs, te->outerAttrs);
566 setAttr(te->attributes);
567 if (te->nonCacheable) {
568 req->setFlags(Request::UNCACHEABLE);
569
570 // Prevent prefetching from I/O devices.
571 if (req->isPrefetch()) {
572 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
573 }
574 }
575
|
584
| 576#if FULL_SYSTEM
|
585 if (!bootUncacheability &&
586 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
587 req->setFlags(Request::UNCACHEABLE);
| 577 if (!bootUncacheability &&
578 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
579 req->setFlags(Request::UNCACHEABLE);
|
| 580#endif
|
588
589 switch ( (dacr >> (te->domain * 2)) & 0x3) {
590 case 0:
591 domainFaults++;
592 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
593 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
594 if (is_fetch)
595 return new PrefetchAbort(vaddr,
596 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
597 else
598 return new DataAbort(vaddr, te->domain, is_write,
599 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
600 case 1:
601 // Continue with permissions check
602 break;
603 case 2:
604 panic("UNPRED domain\n");
605 case 3:
606 req->setPaddr(te->pAddr(vaddr));
607 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
608 if (fault)
609 return fault;
610 return NoFault;
611 }
612
613 uint8_t ap = te->ap;
614
615 if (sctlr.afe == 1)
616 ap |= 1;
617
618 bool abt;
619
620 /* if (!sctlr.xp)
621 ap &= 0x3;
622*/
623 switch (ap) {
624 case 0:
625 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
626 if (!sctlr.xp) {
627 switch ((int)sctlr.rs) {
628 case 2:
629 abt = is_write;
630 break;
631 case 1:
632 abt = is_write || !is_priv;
633 break;
634 case 0:
635 case 3:
636 default:
637 abt = true;
638 break;
639 }
640 } else {
641 abt = true;
642 }
643 break;
644 case 1:
645 abt = !is_priv;
646 break;
647 case 2:
648 abt = !is_priv && is_write;
649 break;
650 case 3:
651 abt = false;
652 break;
653 case 4:
654 panic("UNPRED premissions\n");
655 case 5:
656 abt = !is_priv || is_write;
657 break;
658 case 6:
659 case 7:
660 abt = is_write;
661 break;
662 default:
663 panic("Unknown permissions\n");
664 }
665 if ((is_fetch) && (abt || te->xn)) {
666 permsFaults++;
667 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
668 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
669 return new PrefetchAbort(vaddr,
670 (te->sNp ? ArmFault::Permission0 :
671 ArmFault::Permission1));
672 } else if (abt) {
673 permsFaults++;
674 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
675 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
676 return new DataAbort(vaddr, te->domain, is_write,
677 (te->sNp ? ArmFault::Permission0 :
678 ArmFault::Permission1));
679 }
680
681 req->setPaddr(te->pAddr(vaddr));
682 // Check for a trickbox generated address fault
683 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
684 if (fault)
685 return fault;
686
687 return NoFault;
688}
689
| 581
582 switch ( (dacr >> (te->domain * 2)) & 0x3) {
583 case 0:
584 domainFaults++;
585 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
586 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
587 if (is_fetch)
588 return new PrefetchAbort(vaddr,
589 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
590 else
591 return new DataAbort(vaddr, te->domain, is_write,
592 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
593 case 1:
594 // Continue with permissions check
595 break;
596 case 2:
597 panic("UNPRED domain\n");
598 case 3:
599 req->setPaddr(te->pAddr(vaddr));
600 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
601 if (fault)
602 return fault;
603 return NoFault;
604 }
605
606 uint8_t ap = te->ap;
607
608 if (sctlr.afe == 1)
609 ap |= 1;
610
611 bool abt;
612
613 /* if (!sctlr.xp)
614 ap &= 0x3;
615*/
616 switch (ap) {
617 case 0:
618 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
619 if (!sctlr.xp) {
620 switch ((int)sctlr.rs) {
621 case 2:
622 abt = is_write;
623 break;
624 case 1:
625 abt = is_write || !is_priv;
626 break;
627 case 0:
628 case 3:
629 default:
630 abt = true;
631 break;
632 }
633 } else {
634 abt = true;
635 }
636 break;
637 case 1:
638 abt = !is_priv;
639 break;
640 case 2:
641 abt = !is_priv && is_write;
642 break;
643 case 3:
644 abt = false;
645 break;
646 case 4:
647 panic("UNPRED premissions\n");
648 case 5:
649 abt = !is_priv || is_write;
650 break;
651 case 6:
652 case 7:
653 abt = is_write;
654 break;
655 default:
656 panic("Unknown permissions\n");
657 }
658 if ((is_fetch) && (abt || te->xn)) {
659 permsFaults++;
660 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
661 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
662 return new PrefetchAbort(vaddr,
663 (te->sNp ? ArmFault::Permission0 :
664 ArmFault::Permission1));
665 } else if (abt) {
666 permsFaults++;
667 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
668 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
669 return new DataAbort(vaddr, te->domain, is_write,
670 (te->sNp ? ArmFault::Permission0 :
671 ArmFault::Permission1));
672 }
673
674 req->setPaddr(te->pAddr(vaddr));
675 // Check for a trickbox generated address fault
676 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
677 if (fault)
678 return fault;
679
680 return NoFault;
681}
682
|
690#endif
691
| |
692Fault
693TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
694{
695 bool delay = false;
696 Fault fault;
| 683Fault
684TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
685{
686 bool delay = false;
687 Fault fault;
|
697#if FULL_SYSTEM
698 fault = translateFs(req, tc, mode, NULL, delay, false);
699#else
700 fault = translateSe(req, tc, mode, NULL, delay, false);
701#endif
| 688 if (FullSystem)
689 fault = translateFs(req, tc, mode, NULL, delay, false);
690 else
691 fault = translateSe(req, tc, mode, NULL, delay, false);
|
702 assert(!delay);
703 return fault;
704}
705
706Fault
| 692 assert(!delay);
693 return fault;
694}
695
696Fault
|
707TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
708{
709 bool delay = false;
710 Fault fault;
711#if FULL_SYSTEM
712 fault = translateFs(req, tc, mode, NULL, delay, false, true);
713#else
714 fault = translateSe(req, tc, mode, NULL, delay, false);
715#endif
716 assert(!delay);
717 return fault;
718}
719
720Fault
| |
721TLB::translateTiming(RequestPtr req, ThreadContext *tc,
722 Translation *translation, Mode mode)
723{
724 assert(translation);
725 bool delay = false;
726 Fault fault;
| 697TLB::translateTiming(RequestPtr req, ThreadContext *tc,
698 Translation *translation, Mode mode)
699{
700 assert(translation);
701 bool delay = false;
702 Fault fault;
|
727#if FULL_SYSTEM
728 fault = translateFs(req, tc, mode, translation, delay, true);
729#else
730 fault = translateSe(req, tc, mode, translation, delay, true);
731#endif
| 703 if (FullSystem)
704 fault = translateFs(req, tc, mode, translation, delay, true);
705 else
706 fault = translateSe(req, tc, mode, translation, delay, true);
|
732 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
733 NoFault);
734 if (!delay)
735 translation->finish(fault, req, tc, mode);
736 else
737 translation->markDelayed();
738 return fault;
739}
740
741Port*
742TLB::getPort()
743{
| 707 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
708 NoFault);
709 if (!delay)
710 translation->finish(fault, req, tc, mode);
711 else
712 translation->markDelayed();
713 return fault;
714}
715
716Port*
717TLB::getPort()
718{
|
744#if FULL_SYSTEM
| |
745 return tableWalker->getPort("port");
| 719 return tableWalker->getPort("port");
|
746#else
747 return NULL;
748#endif
| |
749}
750
751
752
753ArmISA::TLB *
754ArmTLBParams::create()
755{
756 return new ArmISA::TLB(this);
757}
| 720}
721
722
723
724ArmISA::TLB *
725ArmTLBParams::create()
726{
727 return new ArmISA::TLB(this);
728}
|