76{ 77 table = new TlbEntry[size]; 78 memset(table, 0, sizeof(TlbEntry) * size); 79 80#if FULL_SYSTEM 81 tableWalker->setTlb(this); 82#endif 83} 84 85TLB::~TLB() 86{ 87 if (table) 88 delete [] table; 89} 90 91bool 92TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 93{ 94 if (!miscRegValid) 95 updateMiscReg(tc); 96 TlbEntry *e = lookup(va, contextId, true); 97 if (!e) 98 return false; 99 pa = e->pAddr(va); 100 return true; 101} 102 103TlbEntry* 104TLB::lookup(Addr va, uint8_t cid, bool functional) 105{ 106 107 TlbEntry *retval = NULL; 108 109 // Maitaining LRU array 110 111 int x = 0; 112 while (retval == NULL && x < size) { 113 if (table[x].match(va, cid)) { 114 115 // We only move the hit entry ahead when the position is higher than rangeMRU 116 if (x > rangeMRU) { 117 TlbEntry tmp_entry = table[x]; 118 for(int i = x; i > 0; i--) 119 table[i] = table[i-1]; 120 table[0] = tmp_entry; 121 retval = &table[0]; 122 } else { 123 retval = &table[x]; 124 } 125 break; 126 } 127 x++; 128 } 129 130 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 131 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 132 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 133 retval ? retval->ap : 0); 134 ; 135 return retval; 136} 137 138// insert a new TLB entry 139void 140TLB::insert(Addr addr, TlbEntry &entry) 141{ 142 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 143 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 144 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 145 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 146 entry.xn, entry.ap, entry.domain); 147 148 if (table[size-1].valid) 149 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 150 table[size-1].vpn << table[size-1].N, table[size-1].asid, 151 table[size-1].pfn << table[size-1].N, table[size-1].size, 152 table[size-1].ap); 153 154 //inserting to MRU position and evicting the LRU one 155 156 for(int i = size-1; i > 0; i--) 157 table[i] = table[i-1]; 158 table[0] = entry; 159 160 inserts++; 161} 162 163void 164TLB::printTlb() 165{ 166 int x = 0; 167 TlbEntry *te; 168 DPRINTF(TLB, "Current TLB contents:\n"); 169 while (x < size) { 170 te = &table[x]; 171 if (te->valid) 172 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 173 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 174 x++; 175 } 176} 177 178 179void 180TLB::flushAll() 181{ 182 DPRINTF(TLB, "Flushing all TLB entries\n"); 183 int x = 0; 184 TlbEntry *te; 185 while (x < size) { 186 te = &table[x]; 187 if (te->valid) { 188 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 189 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 190 flushedEntries++; 191 } 192 x++; 193 } 194 195 memset(table, 0, sizeof(TlbEntry) * size); 196 197 flushTlb++; 198} 199 200 201void 202TLB::flushMvaAsid(Addr mva, uint64_t asn) 203{ 204 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 205 TlbEntry *te; 206 207 te = lookup(mva, asn); 208 while (te != NULL) { 209 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 210 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 211 te->valid = false; 212 flushedEntries++; 213 te = lookup(mva,asn); 214 } 215 flushTlbMvaAsid++; 216} 217 218void 219TLB::flushAsid(uint64_t asn) 220{ 221 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 222 223 int x = 0; 224 TlbEntry *te; 225 226 while (x < size) { 227 te = &table[x]; 228 if (te->asid == asn) { 229 te->valid = false; 230 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 231 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 232 flushedEntries++; 233 } 234 x++; 235 } 236 flushTlbAsid++; 237} 238 239void 240TLB::flushMva(Addr mva) 241{ 242 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 243 244 int x = 0; 245 TlbEntry *te; 246 247 while (x < size) { 248 te = &table[x]; 249 Addr v = te->vpn << te->N; 250 if (mva >= v && mva < v + te->size) { 251 te->valid = false; 252 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 253 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 254 flushedEntries++; 255 } 256 x++; 257 } 258 flushTlbMva++; 259} 260 261void 262TLB::serialize(ostream &os) 263{ 264 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 265 266 SERIALIZE_SCALAR(_attr); 267 268 int num_entries = size; 269 SERIALIZE_SCALAR(num_entries); 270 for(int i = 0; i < size; i++){ 271 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 272 table[i].serialize(os); 273 } 274} 275 276void 277TLB::unserialize(Checkpoint *cp, const string §ion) 278{ 279 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 280 281 UNSERIALIZE_SCALAR(_attr); 282 int num_entries; 283 UNSERIALIZE_SCALAR(num_entries); 284 for(int i = 0; i < min(size, num_entries); i++){ 285 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 286 } 287 miscRegValid = false; 288} 289 290void 291TLB::regStats() 292{ 293 instHits 294 .name(name() + ".inst_hits") 295 .desc("ITB inst hits") 296 ; 297 298 instMisses 299 .name(name() + ".inst_misses") 300 .desc("ITB inst misses") 301 ; 302 303 instAccesses 304 .name(name() + ".inst_accesses") 305 .desc("ITB inst accesses") 306 ; 307 308 readHits 309 .name(name() + ".read_hits") 310 .desc("DTB read hits") 311 ; 312 313 readMisses 314 .name(name() + ".read_misses") 315 .desc("DTB read misses") 316 ; 317 318 readAccesses 319 .name(name() + ".read_accesses") 320 .desc("DTB read accesses") 321 ; 322 323 writeHits 324 .name(name() + ".write_hits") 325 .desc("DTB write hits") 326 ; 327 328 writeMisses 329 .name(name() + ".write_misses") 330 .desc("DTB write misses") 331 ; 332 333 writeAccesses 334 .name(name() + ".write_accesses") 335 .desc("DTB write accesses") 336 ; 337 338 hits 339 .name(name() + ".hits") 340 .desc("DTB hits") 341 ; 342 343 misses 344 .name(name() + ".misses") 345 .desc("DTB misses") 346 ; 347 348 accesses 349 .name(name() + ".accesses") 350 .desc("DTB accesses") 351 ; 352 353 flushTlb 354 .name(name() + ".flush_tlb") 355 .desc("Number of times complete TLB was flushed") 356 ; 357 358 flushTlbMva 359 .name(name() + ".flush_tlb_mva") 360 .desc("Number of times TLB was flushed by MVA") 361 ; 362 363 flushTlbMvaAsid 364 .name(name() + ".flush_tlb_mva_asid") 365 .desc("Number of times TLB was flushed by MVA & ASID") 366 ; 367 368 flushTlbAsid 369 .name(name() + ".flush_tlb_asid") 370 .desc("Number of times TLB was flushed by ASID") 371 ; 372 373 flushedEntries 374 .name(name() + ".flush_entries") 375 .desc("Number of entries that have been flushed from TLB") 376 ; 377 378 alignFaults 379 .name(name() + ".align_faults") 380 .desc("Number of TLB faults due to alignment restrictions") 381 ; 382 383 prefetchFaults 384 .name(name() + ".prefetch_faults") 385 .desc("Number of TLB faults due to prefetch") 386 ; 387 388 domainFaults 389 .name(name() + ".domain_faults") 390 .desc("Number of TLB faults due to domain restrictions") 391 ; 392 393 permsFaults 394 .name(name() + ".perms_faults") 395 .desc("Number of TLB faults due to permissions restrictions") 396 ; 397 398 instAccesses = instHits + instMisses; 399 readAccesses = readHits + readMisses; 400 writeAccesses = writeHits + writeMisses; 401 hits = readHits + writeHits + instHits; 402 misses = readMisses + writeMisses + instMisses; 403 accesses = readAccesses + writeAccesses + instAccesses; 404} 405 406#if !FULL_SYSTEM 407Fault 408TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 409 Translation *translation, bool &delay, bool timing) 410{ 411 if (!miscRegValid) 412 updateMiscReg(tc); 413 Addr vaddr = req->getVaddr(); 414 uint32_t flags = req->getFlags(); 415 416 bool is_fetch = (mode == Execute); 417 bool is_write = (mode == Write); 418 419 if (!is_fetch) { 420 assert(flags & MustBeOne); 421 if (sctlr.a || !(flags & AllowUnaligned)) { 422 if (vaddr & flags & AlignmentMask) { 423 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 424 } 425 } 426 } 427 428 Addr paddr; 429 Process *p = tc->getProcessPtr(); 430 431 if (!p->pTable->translate(vaddr, paddr)) 432 return Fault(new GenericPageTableFault(vaddr)); 433 req->setPaddr(paddr); 434 435 return NoFault; 436} 437 438#else // FULL_SYSTEM 439 440Fault 441TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 442{ 443 return NoFault; 444} 445 446Fault 447TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 448 bool is_write, uint8_t domain, bool sNp) 449{ 450 return NoFault; 451} 452 453Fault 454TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 455 Translation *translation, bool &delay, bool timing) 456{ 457 if (!miscRegValid) { 458 updateMiscReg(tc); 459 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 460 } 461 462 Addr vaddr = req->getVaddr(); 463 uint32_t flags = req->getFlags(); 464 465 bool is_fetch = (mode == Execute); 466 bool is_write = (mode == Write); 467 bool is_priv = isPriv && !(flags & UserMode); 468 469 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 470 isPriv, flags & UserMode); 471 // If this is a clrex instruction, provide a PA of 0 with no fault 472 // This will force the monitor to set the tracked address to 0 473 // a bit of a hack but this effectively clrears this processors monitor 474 if (flags & Request::CLEAR_LL){ 475 req->setPaddr(0); 476 req->setFlags(Request::UNCACHEABLE); 477 req->setFlags(Request::CLEAR_LL); 478 return NoFault; 479 } 480 if ((req->isInstFetch() && (!sctlr.i)) || 481 ((!req->isInstFetch()) && (!sctlr.c))){ 482 req->setFlags(Request::UNCACHEABLE); 483 } 484 if (!is_fetch) { 485 assert(flags & MustBeOne); 486 if (sctlr.a || !(flags & AllowUnaligned)) { 487 if (vaddr & flags & AlignmentMask) { 488 alignFaults++; 489 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 490 } 491 } 492 } 493 494 Fault fault; 495 496 if (!sctlr.m) { 497 req->setPaddr(vaddr); 498 if (sctlr.tre == 0) { 499 req->setFlags(Request::UNCACHEABLE); 500 } else { 501 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 502 req->setFlags(Request::UNCACHEABLE); 503 } 504 505 // Set memory attributes 506 TlbEntry temp_te; 507 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 508 temp_te.shareable = true; 509 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 510 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 511 temp_te.innerAttrs, temp_te.outerAttrs); 512 setAttr(temp_te.attributes); 513 514 return trickBoxCheck(req, mode, 0, false); 515 } 516 517 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 518 // Translation enabled 519 520 TlbEntry *te = lookup(vaddr, contextId); 521 if (te == NULL) { 522 if (req->isPrefetch()){ 523 //if the request is a prefetch don't attempt to fill the TLB 524 //or go any further with the memory access 525 prefetchFaults++; 526 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 527 } 528 529 if (is_fetch) 530 instMisses++; 531 else if (is_write) 532 writeMisses++; 533 else 534 readMisses++; 535 536 // start translation table walk, pass variables rather than 537 // re-retreaving in table walker for speed 538 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 539 vaddr, contextId); 540 fault = tableWalker->walk(req, tc, contextId, mode, translation, 541 timing); 542 if (timing && fault == NoFault) { 543 delay = true; 544 // for timing mode, return and wait for table walk 545 return fault; 546 } 547 if (fault) 548 return fault; 549 550 te = lookup(vaddr, contextId); 551 if (!te) 552 printTlb(); 553 assert(te); 554 } else { 555 if (is_fetch) 556 instHits++; 557 else if (is_write) 558 writeHits++; 559 else 560 readHits++; 561 } 562 563 // Set memory attributes 564 DPRINTF(TLBVerbose, 565 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 566 outerAttrs: %d\n", 567 te->shareable, te->innerAttrs, te->outerAttrs); 568 setAttr(te->attributes); 569 if (te->nonCacheable) { 570 req->setFlags(Request::UNCACHEABLE); 571 572 // Prevent prefetching from I/O devices. 573 if (req->isPrefetch()) { 574 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 575 } 576 } 577
| 77{ 78 table = new TlbEntry[size]; 79 memset(table, 0, sizeof(TlbEntry) * size); 80 81#if FULL_SYSTEM 82 tableWalker->setTlb(this); 83#endif 84} 85 86TLB::~TLB() 87{ 88 if (table) 89 delete [] table; 90} 91 92bool 93TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 94{ 95 if (!miscRegValid) 96 updateMiscReg(tc); 97 TlbEntry *e = lookup(va, contextId, true); 98 if (!e) 99 return false; 100 pa = e->pAddr(va); 101 return true; 102} 103 104TlbEntry* 105TLB::lookup(Addr va, uint8_t cid, bool functional) 106{ 107 108 TlbEntry *retval = NULL; 109 110 // Maitaining LRU array 111 112 int x = 0; 113 while (retval == NULL && x < size) { 114 if (table[x].match(va, cid)) { 115 116 // We only move the hit entry ahead when the position is higher than rangeMRU 117 if (x > rangeMRU) { 118 TlbEntry tmp_entry = table[x]; 119 for(int i = x; i > 0; i--) 120 table[i] = table[i-1]; 121 table[0] = tmp_entry; 122 retval = &table[0]; 123 } else { 124 retval = &table[x]; 125 } 126 break; 127 } 128 x++; 129 } 130 131 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 132 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 133 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 134 retval ? retval->ap : 0); 135 ; 136 return retval; 137} 138 139// insert a new TLB entry 140void 141TLB::insert(Addr addr, TlbEntry &entry) 142{ 143 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 144 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 145 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 146 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 147 entry.xn, entry.ap, entry.domain); 148 149 if (table[size-1].valid) 150 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 151 table[size-1].vpn << table[size-1].N, table[size-1].asid, 152 table[size-1].pfn << table[size-1].N, table[size-1].size, 153 table[size-1].ap); 154 155 //inserting to MRU position and evicting the LRU one 156 157 for(int i = size-1; i > 0; i--) 158 table[i] = table[i-1]; 159 table[0] = entry; 160 161 inserts++; 162} 163 164void 165TLB::printTlb() 166{ 167 int x = 0; 168 TlbEntry *te; 169 DPRINTF(TLB, "Current TLB contents:\n"); 170 while (x < size) { 171 te = &table[x]; 172 if (te->valid) 173 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 174 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 175 x++; 176 } 177} 178 179 180void 181TLB::flushAll() 182{ 183 DPRINTF(TLB, "Flushing all TLB entries\n"); 184 int x = 0; 185 TlbEntry *te; 186 while (x < size) { 187 te = &table[x]; 188 if (te->valid) { 189 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 190 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 191 flushedEntries++; 192 } 193 x++; 194 } 195 196 memset(table, 0, sizeof(TlbEntry) * size); 197 198 flushTlb++; 199} 200 201 202void 203TLB::flushMvaAsid(Addr mva, uint64_t asn) 204{ 205 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 206 TlbEntry *te; 207 208 te = lookup(mva, asn); 209 while (te != NULL) { 210 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 211 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 212 te->valid = false; 213 flushedEntries++; 214 te = lookup(mva,asn); 215 } 216 flushTlbMvaAsid++; 217} 218 219void 220TLB::flushAsid(uint64_t asn) 221{ 222 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 223 224 int x = 0; 225 TlbEntry *te; 226 227 while (x < size) { 228 te = &table[x]; 229 if (te->asid == asn) { 230 te->valid = false; 231 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 232 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 233 flushedEntries++; 234 } 235 x++; 236 } 237 flushTlbAsid++; 238} 239 240void 241TLB::flushMva(Addr mva) 242{ 243 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 244 245 int x = 0; 246 TlbEntry *te; 247 248 while (x < size) { 249 te = &table[x]; 250 Addr v = te->vpn << te->N; 251 if (mva >= v && mva < v + te->size) { 252 te->valid = false; 253 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 254 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 255 flushedEntries++; 256 } 257 x++; 258 } 259 flushTlbMva++; 260} 261 262void 263TLB::serialize(ostream &os) 264{ 265 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 266 267 SERIALIZE_SCALAR(_attr); 268 269 int num_entries = size; 270 SERIALIZE_SCALAR(num_entries); 271 for(int i = 0; i < size; i++){ 272 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 273 table[i].serialize(os); 274 } 275} 276 277void 278TLB::unserialize(Checkpoint *cp, const string §ion) 279{ 280 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 281 282 UNSERIALIZE_SCALAR(_attr); 283 int num_entries; 284 UNSERIALIZE_SCALAR(num_entries); 285 for(int i = 0; i < min(size, num_entries); i++){ 286 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 287 } 288 miscRegValid = false; 289} 290 291void 292TLB::regStats() 293{ 294 instHits 295 .name(name() + ".inst_hits") 296 .desc("ITB inst hits") 297 ; 298 299 instMisses 300 .name(name() + ".inst_misses") 301 .desc("ITB inst misses") 302 ; 303 304 instAccesses 305 .name(name() + ".inst_accesses") 306 .desc("ITB inst accesses") 307 ; 308 309 readHits 310 .name(name() + ".read_hits") 311 .desc("DTB read hits") 312 ; 313 314 readMisses 315 .name(name() + ".read_misses") 316 .desc("DTB read misses") 317 ; 318 319 readAccesses 320 .name(name() + ".read_accesses") 321 .desc("DTB read accesses") 322 ; 323 324 writeHits 325 .name(name() + ".write_hits") 326 .desc("DTB write hits") 327 ; 328 329 writeMisses 330 .name(name() + ".write_misses") 331 .desc("DTB write misses") 332 ; 333 334 writeAccesses 335 .name(name() + ".write_accesses") 336 .desc("DTB write accesses") 337 ; 338 339 hits 340 .name(name() + ".hits") 341 .desc("DTB hits") 342 ; 343 344 misses 345 .name(name() + ".misses") 346 .desc("DTB misses") 347 ; 348 349 accesses 350 .name(name() + ".accesses") 351 .desc("DTB accesses") 352 ; 353 354 flushTlb 355 .name(name() + ".flush_tlb") 356 .desc("Number of times complete TLB was flushed") 357 ; 358 359 flushTlbMva 360 .name(name() + ".flush_tlb_mva") 361 .desc("Number of times TLB was flushed by MVA") 362 ; 363 364 flushTlbMvaAsid 365 .name(name() + ".flush_tlb_mva_asid") 366 .desc("Number of times TLB was flushed by MVA & ASID") 367 ; 368 369 flushTlbAsid 370 .name(name() + ".flush_tlb_asid") 371 .desc("Number of times TLB was flushed by ASID") 372 ; 373 374 flushedEntries 375 .name(name() + ".flush_entries") 376 .desc("Number of entries that have been flushed from TLB") 377 ; 378 379 alignFaults 380 .name(name() + ".align_faults") 381 .desc("Number of TLB faults due to alignment restrictions") 382 ; 383 384 prefetchFaults 385 .name(name() + ".prefetch_faults") 386 .desc("Number of TLB faults due to prefetch") 387 ; 388 389 domainFaults 390 .name(name() + ".domain_faults") 391 .desc("Number of TLB faults due to domain restrictions") 392 ; 393 394 permsFaults 395 .name(name() + ".perms_faults") 396 .desc("Number of TLB faults due to permissions restrictions") 397 ; 398 399 instAccesses = instHits + instMisses; 400 readAccesses = readHits + readMisses; 401 writeAccesses = writeHits + writeMisses; 402 hits = readHits + writeHits + instHits; 403 misses = readMisses + writeMisses + instMisses; 404 accesses = readAccesses + writeAccesses + instAccesses; 405} 406 407#if !FULL_SYSTEM 408Fault 409TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 410 Translation *translation, bool &delay, bool timing) 411{ 412 if (!miscRegValid) 413 updateMiscReg(tc); 414 Addr vaddr = req->getVaddr(); 415 uint32_t flags = req->getFlags(); 416 417 bool is_fetch = (mode == Execute); 418 bool is_write = (mode == Write); 419 420 if (!is_fetch) { 421 assert(flags & MustBeOne); 422 if (sctlr.a || !(flags & AllowUnaligned)) { 423 if (vaddr & flags & AlignmentMask) { 424 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 425 } 426 } 427 } 428 429 Addr paddr; 430 Process *p = tc->getProcessPtr(); 431 432 if (!p->pTable->translate(vaddr, paddr)) 433 return Fault(new GenericPageTableFault(vaddr)); 434 req->setPaddr(paddr); 435 436 return NoFault; 437} 438 439#else // FULL_SYSTEM 440 441Fault 442TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 443{ 444 return NoFault; 445} 446 447Fault 448TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 449 bool is_write, uint8_t domain, bool sNp) 450{ 451 return NoFault; 452} 453 454Fault 455TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 456 Translation *translation, bool &delay, bool timing) 457{ 458 if (!miscRegValid) { 459 updateMiscReg(tc); 460 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 461 } 462 463 Addr vaddr = req->getVaddr(); 464 uint32_t flags = req->getFlags(); 465 466 bool is_fetch = (mode == Execute); 467 bool is_write = (mode == Write); 468 bool is_priv = isPriv && !(flags & UserMode); 469 470 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 471 isPriv, flags & UserMode); 472 // If this is a clrex instruction, provide a PA of 0 with no fault 473 // This will force the monitor to set the tracked address to 0 474 // a bit of a hack but this effectively clrears this processors monitor 475 if (flags & Request::CLEAR_LL){ 476 req->setPaddr(0); 477 req->setFlags(Request::UNCACHEABLE); 478 req->setFlags(Request::CLEAR_LL); 479 return NoFault; 480 } 481 if ((req->isInstFetch() && (!sctlr.i)) || 482 ((!req->isInstFetch()) && (!sctlr.c))){ 483 req->setFlags(Request::UNCACHEABLE); 484 } 485 if (!is_fetch) { 486 assert(flags & MustBeOne); 487 if (sctlr.a || !(flags & AllowUnaligned)) { 488 if (vaddr & flags & AlignmentMask) { 489 alignFaults++; 490 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 491 } 492 } 493 } 494 495 Fault fault; 496 497 if (!sctlr.m) { 498 req->setPaddr(vaddr); 499 if (sctlr.tre == 0) { 500 req->setFlags(Request::UNCACHEABLE); 501 } else { 502 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 503 req->setFlags(Request::UNCACHEABLE); 504 } 505 506 // Set memory attributes 507 TlbEntry temp_te; 508 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 509 temp_te.shareable = true; 510 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 511 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 512 temp_te.innerAttrs, temp_te.outerAttrs); 513 setAttr(temp_te.attributes); 514 515 return trickBoxCheck(req, mode, 0, false); 516 } 517 518 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 519 // Translation enabled 520 521 TlbEntry *te = lookup(vaddr, contextId); 522 if (te == NULL) { 523 if (req->isPrefetch()){ 524 //if the request is a prefetch don't attempt to fill the TLB 525 //or go any further with the memory access 526 prefetchFaults++; 527 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 528 } 529 530 if (is_fetch) 531 instMisses++; 532 else if (is_write) 533 writeMisses++; 534 else 535 readMisses++; 536 537 // start translation table walk, pass variables rather than 538 // re-retreaving in table walker for speed 539 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 540 vaddr, contextId); 541 fault = tableWalker->walk(req, tc, contextId, mode, translation, 542 timing); 543 if (timing && fault == NoFault) { 544 delay = true; 545 // for timing mode, return and wait for table walk 546 return fault; 547 } 548 if (fault) 549 return fault; 550 551 te = lookup(vaddr, contextId); 552 if (!te) 553 printTlb(); 554 assert(te); 555 } else { 556 if (is_fetch) 557 instHits++; 558 else if (is_write) 559 writeHits++; 560 else 561 readHits++; 562 } 563 564 // Set memory attributes 565 DPRINTF(TLBVerbose, 566 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 567 outerAttrs: %d\n", 568 te->shareable, te->innerAttrs, te->outerAttrs); 569 setAttr(te->attributes); 570 if (te->nonCacheable) { 571 req->setFlags(Request::UNCACHEABLE); 572 573 // Prevent prefetching from I/O devices. 574 if (req->isPrefetch()) { 575 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 576 } 577 } 578
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578 switch ( (dacr >> (te->domain * 2)) & 0x3) { 579 case 0: 580 domainFaults++; 581 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 582 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 583 if (is_fetch) 584 return new PrefetchAbort(vaddr, 585 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 586 else 587 return new DataAbort(vaddr, te->domain, is_write, 588 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 589 case 1: 590 // Continue with permissions check 591 break; 592 case 2: 593 panic("UNPRED domain\n"); 594 case 3: 595 req->setPaddr(te->pAddr(vaddr)); 596 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 597 if (fault) 598 return fault; 599 return NoFault; 600 } 601 602 uint8_t ap = te->ap; 603 604 if (sctlr.afe == 1) 605 ap |= 1; 606 607 bool abt; 608 609 /* if (!sctlr.xp) 610 ap &= 0x3; 611*/ 612 switch (ap) { 613 case 0: 614 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 615 if (!sctlr.xp) { 616 switch ((int)sctlr.rs) { 617 case 2: 618 abt = is_write; 619 break; 620 case 1: 621 abt = is_write || !is_priv; 622 break; 623 case 0: 624 case 3: 625 default: 626 abt = true; 627 break; 628 } 629 } else { 630 abt = true; 631 } 632 break; 633 case 1: 634 abt = !is_priv; 635 break; 636 case 2: 637 abt = !is_priv && is_write; 638 break; 639 case 3: 640 abt = false; 641 break; 642 case 4: 643 panic("UNPRED premissions\n"); 644 case 5: 645 abt = !is_priv || is_write; 646 break; 647 case 6: 648 case 7: 649 abt = is_write; 650 break; 651 default: 652 panic("Unknown permissions\n"); 653 } 654 if ((is_fetch) && (abt || te->xn)) { 655 permsFaults++; 656 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 657 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 658 return new PrefetchAbort(vaddr, 659 (te->sNp ? ArmFault::Permission0 : 660 ArmFault::Permission1)); 661 } else if (abt) { 662 permsFaults++; 663 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 664 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 665 return new DataAbort(vaddr, te->domain, is_write, 666 (te->sNp ? ArmFault::Permission0 : 667 ArmFault::Permission1)); 668 } 669 670 req->setPaddr(te->pAddr(vaddr)); 671 // Check for a trickbox generated address fault 672 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 673 if (fault) 674 return fault; 675 676 return NoFault; 677} 678 679#endif 680 681Fault 682TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 683{ 684 bool delay = false; 685 Fault fault; 686#if FULL_SYSTEM 687 fault = translateFs(req, tc, mode, NULL, delay, false); 688#else 689 fault = translateSe(req, tc, mode, NULL, delay, false); 690#endif 691 assert(!delay); 692 return fault; 693} 694 695Fault 696TLB::translateTiming(RequestPtr req, ThreadContext *tc, 697 Translation *translation, Mode mode) 698{ 699 assert(translation); 700 bool delay = false; 701 Fault fault; 702#if FULL_SYSTEM 703 fault = translateFs(req, tc, mode, translation, delay, true); 704#else 705 fault = translateSe(req, tc, mode, translation, delay, true); 706#endif
| 584 switch ( (dacr >> (te->domain * 2)) & 0x3) { 585 case 0: 586 domainFaults++; 587 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 588 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 589 if (is_fetch) 590 return new PrefetchAbort(vaddr, 591 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 592 else 593 return new DataAbort(vaddr, te->domain, is_write, 594 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 595 case 1: 596 // Continue with permissions check 597 break; 598 case 2: 599 panic("UNPRED domain\n"); 600 case 3: 601 req->setPaddr(te->pAddr(vaddr)); 602 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 603 if (fault) 604 return fault; 605 return NoFault; 606 } 607 608 uint8_t ap = te->ap; 609 610 if (sctlr.afe == 1) 611 ap |= 1; 612 613 bool abt; 614 615 /* if (!sctlr.xp) 616 ap &= 0x3; 617*/ 618 switch (ap) { 619 case 0: 620 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 621 if (!sctlr.xp) { 622 switch ((int)sctlr.rs) { 623 case 2: 624 abt = is_write; 625 break; 626 case 1: 627 abt = is_write || !is_priv; 628 break; 629 case 0: 630 case 3: 631 default: 632 abt = true; 633 break; 634 } 635 } else { 636 abt = true; 637 } 638 break; 639 case 1: 640 abt = !is_priv; 641 break; 642 case 2: 643 abt = !is_priv && is_write; 644 break; 645 case 3: 646 abt = false; 647 break; 648 case 4: 649 panic("UNPRED premissions\n"); 650 case 5: 651 abt = !is_priv || is_write; 652 break; 653 case 6: 654 case 7: 655 abt = is_write; 656 break; 657 default: 658 panic("Unknown permissions\n"); 659 } 660 if ((is_fetch) && (abt || te->xn)) { 661 permsFaults++; 662 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 663 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 664 return new PrefetchAbort(vaddr, 665 (te->sNp ? ArmFault::Permission0 : 666 ArmFault::Permission1)); 667 } else if (abt) { 668 permsFaults++; 669 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 670 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 671 return new DataAbort(vaddr, te->domain, is_write, 672 (te->sNp ? ArmFault::Permission0 : 673 ArmFault::Permission1)); 674 } 675 676 req->setPaddr(te->pAddr(vaddr)); 677 // Check for a trickbox generated address fault 678 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 679 if (fault) 680 return fault; 681 682 return NoFault; 683} 684 685#endif 686 687Fault 688TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 689{ 690 bool delay = false; 691 Fault fault; 692#if FULL_SYSTEM 693 fault = translateFs(req, tc, mode, NULL, delay, false); 694#else 695 fault = translateSe(req, tc, mode, NULL, delay, false); 696#endif 697 assert(!delay); 698 return fault; 699} 700 701Fault 702TLB::translateTiming(RequestPtr req, ThreadContext *tc, 703 Translation *translation, Mode mode) 704{ 705 assert(translation); 706 bool delay = false; 707 Fault fault; 708#if FULL_SYSTEM 709 fault = translateFs(req, tc, mode, translation, delay, true); 710#else 711 fault = translateSe(req, tc, mode, translation, delay, true); 712#endif
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