tlb.cc (8232:b28d06a175be) tlb.cc (8352:9a3c002dab3e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Checkpoint.hh"
57#include "debug/TLB.hh"
58#include "debug/TLBVerbose.hh"
59#include "mem/page_table.hh"
60#include "params/ArmTLB.hh"
61#include "sim/process.hh"
62
63#if FULL_SYSTEM
64#include "arch/arm/table_walker.hh"
65#endif
66
67using namespace std;
68using namespace ArmISA;
69
70TLB::TLB(const Params *p)
71 : BaseTLB(p), size(p->size)
72#if FULL_SYSTEM
73 , tableWalker(p->walker)
74#endif
75 , rangeMRU(1), miscRegValid(false)
76{
77 table = new TlbEntry[size];
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Checkpoint.hh"
57#include "debug/TLB.hh"
58#include "debug/TLBVerbose.hh"
59#include "mem/page_table.hh"
60#include "params/ArmTLB.hh"
61#include "sim/process.hh"
62
63#if FULL_SYSTEM
64#include "arch/arm/table_walker.hh"
65#endif
66
67using namespace std;
68using namespace ArmISA;
69
70TLB::TLB(const Params *p)
71 : BaseTLB(p), size(p->size)
72#if FULL_SYSTEM
73 , tableWalker(p->walker)
74#endif
75 , rangeMRU(1), miscRegValid(false)
76{
77 table = new TlbEntry[size];
78 memset(table, 0, sizeof(TlbEntry[size]));
78 memset(table, 0, sizeof(TlbEntry) * size);
79
80#if FULL_SYSTEM
81 tableWalker->setTlb(this);
82#endif
83}
84
85TLB::~TLB()
86{
87 if (table)
88 delete [] table;
89}
90
91bool
92TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
93{
94 if (!miscRegValid)
95 updateMiscReg(tc);
96 TlbEntry *e = lookup(va, contextId, true);
97 if (!e)
98 return false;
99 pa = e->pAddr(va);
100 return true;
101}
102
103TlbEntry*
104TLB::lookup(Addr va, uint8_t cid, bool functional)
105{
106
107 TlbEntry *retval = NULL;
108
109 // Maitaining LRU array
110
111 int x = 0;
112 while (retval == NULL && x < size) {
113 if (table[x].match(va, cid)) {
114
115 // We only move the hit entry ahead when the position is higher than rangeMRU
116 if (x > rangeMRU) {
117 TlbEntry tmp_entry = table[x];
118 for(int i = x; i > 0; i--)
119 table[i] = table[i-1];
120 table[0] = tmp_entry;
121 retval = &table[0];
122 } else {
123 retval = &table[x];
124 }
125 break;
126 }
127 x++;
128 }
129
130 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
131 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
132 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
133 retval ? retval->ap : 0);
134 ;
135 return retval;
136}
137
138// insert a new TLB entry
139void
140TLB::insert(Addr addr, TlbEntry &entry)
141{
142 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
143 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
144 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
145 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
146 entry.xn, entry.ap, entry.domain);
147
148 if (table[size-1].valid)
149 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
150 table[size-1].vpn << table[size-1].N, table[size-1].asid,
151 table[size-1].pfn << table[size-1].N, table[size-1].size,
152 table[size-1].ap);
153
154 //inserting to MRU position and evicting the LRU one
155
156 for(int i = size-1; i > 0; i--)
157 table[i] = table[i-1];
158 table[0] = entry;
159
160 inserts++;
161}
162
163void
164TLB::printTlb()
165{
166 int x = 0;
167 TlbEntry *te;
168 DPRINTF(TLB, "Current TLB contents:\n");
169 while (x < size) {
170 te = &table[x];
171 if (te->valid)
172 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
173 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
174 x++;
175 }
176}
177
178
179void
180TLB::flushAll()
181{
182 DPRINTF(TLB, "Flushing all TLB entries\n");
183 int x = 0;
184 TlbEntry *te;
185 while (x < size) {
186 te = &table[x];
187 if (te->valid) {
188 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
189 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
190 flushedEntries++;
191 }
192 x++;
193 }
194
79
80#if FULL_SYSTEM
81 tableWalker->setTlb(this);
82#endif
83}
84
85TLB::~TLB()
86{
87 if (table)
88 delete [] table;
89}
90
91bool
92TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
93{
94 if (!miscRegValid)
95 updateMiscReg(tc);
96 TlbEntry *e = lookup(va, contextId, true);
97 if (!e)
98 return false;
99 pa = e->pAddr(va);
100 return true;
101}
102
103TlbEntry*
104TLB::lookup(Addr va, uint8_t cid, bool functional)
105{
106
107 TlbEntry *retval = NULL;
108
109 // Maitaining LRU array
110
111 int x = 0;
112 while (retval == NULL && x < size) {
113 if (table[x].match(va, cid)) {
114
115 // We only move the hit entry ahead when the position is higher than rangeMRU
116 if (x > rangeMRU) {
117 TlbEntry tmp_entry = table[x];
118 for(int i = x; i > 0; i--)
119 table[i] = table[i-1];
120 table[0] = tmp_entry;
121 retval = &table[0];
122 } else {
123 retval = &table[x];
124 }
125 break;
126 }
127 x++;
128 }
129
130 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
131 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
132 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
133 retval ? retval->ap : 0);
134 ;
135 return retval;
136}
137
138// insert a new TLB entry
139void
140TLB::insert(Addr addr, TlbEntry &entry)
141{
142 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
143 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
144 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
145 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
146 entry.xn, entry.ap, entry.domain);
147
148 if (table[size-1].valid)
149 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
150 table[size-1].vpn << table[size-1].N, table[size-1].asid,
151 table[size-1].pfn << table[size-1].N, table[size-1].size,
152 table[size-1].ap);
153
154 //inserting to MRU position and evicting the LRU one
155
156 for(int i = size-1; i > 0; i--)
157 table[i] = table[i-1];
158 table[0] = entry;
159
160 inserts++;
161}
162
163void
164TLB::printTlb()
165{
166 int x = 0;
167 TlbEntry *te;
168 DPRINTF(TLB, "Current TLB contents:\n");
169 while (x < size) {
170 te = &table[x];
171 if (te->valid)
172 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
173 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
174 x++;
175 }
176}
177
178
179void
180TLB::flushAll()
181{
182 DPRINTF(TLB, "Flushing all TLB entries\n");
183 int x = 0;
184 TlbEntry *te;
185 while (x < size) {
186 te = &table[x];
187 if (te->valid) {
188 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
189 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
190 flushedEntries++;
191 }
192 x++;
193 }
194
195 memset(table, 0, sizeof(TlbEntry[size]));
195 memset(table, 0, sizeof(TlbEntry) * size);
196
197 flushTlb++;
198}
199
200
201void
202TLB::flushMvaAsid(Addr mva, uint64_t asn)
203{
204 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
205 TlbEntry *te;
206
207 te = lookup(mva, asn);
208 while (te != NULL) {
209 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
210 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
211 te->valid = false;
212 flushedEntries++;
213 te = lookup(mva,asn);
214 }
215 flushTlbMvaAsid++;
216}
217
218void
219TLB::flushAsid(uint64_t asn)
220{
221 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
222
223 int x = 0;
224 TlbEntry *te;
225
226 while (x < size) {
227 te = &table[x];
228 if (te->asid == asn) {
229 te->valid = false;
230 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
231 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
232 flushedEntries++;
233 }
234 x++;
235 }
236 flushTlbAsid++;
237}
238
239void
240TLB::flushMva(Addr mva)
241{
242 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
243
244 int x = 0;
245 TlbEntry *te;
246
247 while (x < size) {
248 te = &table[x];
249 Addr v = te->vpn << te->N;
250 if (mva >= v && mva < v + te->size) {
251 te->valid = false;
252 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
253 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
254 flushedEntries++;
255 }
256 x++;
257 }
258 flushTlbMva++;
259}
260
261void
262TLB::serialize(ostream &os)
263{
264 DPRINTF(Checkpoint, "Serializing Arm TLB\n");
265
266 SERIALIZE_SCALAR(_attr);
267 for(int i = 0; i < size; i++){
268 nameOut(os, csprintf("%s.TlbEntry%d", name(), i));
269 table[i].serialize(os);
270 }
271}
272
273void
274TLB::unserialize(Checkpoint *cp, const string &section)
275{
276 DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
277
278 UNSERIALIZE_SCALAR(_attr);
279 for(int i = 0; i < size; i++){
280 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
281 }
282 miscRegValid = false;
283}
284
285void
286TLB::regStats()
287{
288 instHits
289 .name(name() + ".inst_hits")
290 .desc("ITB inst hits")
291 ;
292
293 instMisses
294 .name(name() + ".inst_misses")
295 .desc("ITB inst misses")
296 ;
297
298 instAccesses
299 .name(name() + ".inst_accesses")
300 .desc("ITB inst accesses")
301 ;
302
303 readHits
304 .name(name() + ".read_hits")
305 .desc("DTB read hits")
306 ;
307
308 readMisses
309 .name(name() + ".read_misses")
310 .desc("DTB read misses")
311 ;
312
313 readAccesses
314 .name(name() + ".read_accesses")
315 .desc("DTB read accesses")
316 ;
317
318 writeHits
319 .name(name() + ".write_hits")
320 .desc("DTB write hits")
321 ;
322
323 writeMisses
324 .name(name() + ".write_misses")
325 .desc("DTB write misses")
326 ;
327
328 writeAccesses
329 .name(name() + ".write_accesses")
330 .desc("DTB write accesses")
331 ;
332
333 hits
334 .name(name() + ".hits")
335 .desc("DTB hits")
336 ;
337
338 misses
339 .name(name() + ".misses")
340 .desc("DTB misses")
341 ;
342
343 accesses
344 .name(name() + ".accesses")
345 .desc("DTB accesses")
346 ;
347
348 flushTlb
349 .name(name() + ".flush_tlb")
350 .desc("Number of times complete TLB was flushed")
351 ;
352
353 flushTlbMva
354 .name(name() + ".flush_tlb_mva")
355 .desc("Number of times TLB was flushed by MVA")
356 ;
357
358 flushTlbMvaAsid
359 .name(name() + ".flush_tlb_mva_asid")
360 .desc("Number of times TLB was flushed by MVA & ASID")
361 ;
362
363 flushTlbAsid
364 .name(name() + ".flush_tlb_asid")
365 .desc("Number of times TLB was flushed by ASID")
366 ;
367
368 flushedEntries
369 .name(name() + ".flush_entries")
370 .desc("Number of entries that have been flushed from TLB")
371 ;
372
373 alignFaults
374 .name(name() + ".align_faults")
375 .desc("Number of TLB faults due to alignment restrictions")
376 ;
377
378 prefetchFaults
379 .name(name() + ".prefetch_faults")
380 .desc("Number of TLB faults due to prefetch")
381 ;
382
383 domainFaults
384 .name(name() + ".domain_faults")
385 .desc("Number of TLB faults due to domain restrictions")
386 ;
387
388 permsFaults
389 .name(name() + ".perms_faults")
390 .desc("Number of TLB faults due to permissions restrictions")
391 ;
392
393 instAccesses = instHits + instMisses;
394 readAccesses = readHits + readMisses;
395 writeAccesses = writeHits + writeMisses;
396 hits = readHits + writeHits + instHits;
397 misses = readMisses + writeMisses + instMisses;
398 accesses = readAccesses + writeAccesses + instAccesses;
399}
400
401#if !FULL_SYSTEM
402Fault
403TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
404 Translation *translation, bool &delay, bool timing)
405{
406 if (!miscRegValid)
407 updateMiscReg(tc);
408 Addr vaddr = req->getVaddr();
409 uint32_t flags = req->getFlags();
410
411 bool is_fetch = (mode == Execute);
412 bool is_write = (mode == Write);
413
414 if (!is_fetch) {
415 assert(flags & MustBeOne);
416 if (sctlr.a || !(flags & AllowUnaligned)) {
417 if (vaddr & flags & AlignmentMask) {
418 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
419 }
420 }
421 }
422
423 Addr paddr;
424 Process *p = tc->getProcessPtr();
425
426 if (!p->pTable->translate(vaddr, paddr))
427 return Fault(new GenericPageTableFault(vaddr));
428 req->setPaddr(paddr);
429
430 return NoFault;
431}
432
433#else // FULL_SYSTEM
434
435Fault
436TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
437{
438 return NoFault;
439}
440
441Fault
442TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
443 bool is_write, uint8_t domain, bool sNp)
444{
445 return NoFault;
446}
447
448Fault
449TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
450 Translation *translation, bool &delay, bool timing)
451{
452 if (!miscRegValid) {
453 updateMiscReg(tc);
454 DPRINTF(TLBVerbose, "TLB variables changed!\n");
455 }
456
457 Addr vaddr = req->getVaddr();
458 uint32_t flags = req->getFlags();
459
460 bool is_fetch = (mode == Execute);
461 bool is_write = (mode == Write);
462 bool is_priv = isPriv && !(flags & UserMode);
463
464 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
465 isPriv, flags & UserMode);
466 // If this is a clrex instruction, provide a PA of 0 with no fault
467 // This will force the monitor to set the tracked address to 0
468 // a bit of a hack but this effectively clrears this processors monitor
469 if (flags & Request::CLEAR_LL){
470 req->setPaddr(0);
471 req->setFlags(Request::UNCACHEABLE);
472 req->setFlags(Request::CLEAR_LL);
473 return NoFault;
474 }
475 if ((req->isInstFetch() && (!sctlr.i)) ||
476 ((!req->isInstFetch()) && (!sctlr.c))){
477 req->setFlags(Request::UNCACHEABLE);
478 }
479 if (!is_fetch) {
480 assert(flags & MustBeOne);
481 if (sctlr.a || !(flags & AllowUnaligned)) {
482 if (vaddr & flags & AlignmentMask) {
483 alignFaults++;
484 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
485 }
486 }
487 }
488
489 Fault fault;
490
491 if (!sctlr.m) {
492 req->setPaddr(vaddr);
493 if (sctlr.tre == 0) {
494 req->setFlags(Request::UNCACHEABLE);
495 } else {
496 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
497 req->setFlags(Request::UNCACHEABLE);
498 }
499
500 // Set memory attributes
501 TlbEntry temp_te;
502 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
503 temp_te.shareable = true;
504 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
505 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
506 temp_te.innerAttrs, temp_te.outerAttrs);
507 setAttr(temp_te.attributes);
508
509 return trickBoxCheck(req, mode, 0, false);
510 }
511
512 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId);
513 // Translation enabled
514
515 TlbEntry *te = lookup(vaddr, contextId);
516 if (te == NULL) {
517 if (req->isPrefetch()){
518 //if the request is a prefetch don't attempt to fill the TLB
519 //or go any further with the memory access
520 prefetchFaults++;
521 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
522 }
523
524 if (is_fetch)
525 instMisses++;
526 else if (is_write)
527 writeMisses++;
528 else
529 readMisses++;
530
531 // start translation table walk, pass variables rather than
532 // re-retreaving in table walker for speed
533 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
534 vaddr, contextId);
535 fault = tableWalker->walk(req, tc, contextId, mode, translation,
536 timing);
537 if (timing && fault == NoFault) {
538 delay = true;
539 // for timing mode, return and wait for table walk
540 return fault;
541 }
542 if (fault)
543 return fault;
544
545 te = lookup(vaddr, contextId);
546 if (!te)
547 printTlb();
548 assert(te);
549 } else {
550 if (is_fetch)
551 instHits++;
552 else if (is_write)
553 writeHits++;
554 else
555 readHits++;
556 }
557
558 // Set memory attributes
559 DPRINTF(TLBVerbose,
560 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
561 outerAttrs: %d\n",
562 te->shareable, te->innerAttrs, te->outerAttrs);
563 setAttr(te->attributes);
564 if (te->nonCacheable) {
565 req->setFlags(Request::UNCACHEABLE);
566
567 // Prevent prefetching from I/O devices.
568 if (req->isPrefetch()) {
569 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
570 }
571 }
572
573 switch ( (dacr >> (te->domain * 2)) & 0x3) {
574 case 0:
575 domainFaults++;
576 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
577 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
578 if (is_fetch)
579 return new PrefetchAbort(vaddr,
580 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
581 else
582 return new DataAbort(vaddr, te->domain, is_write,
583 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
584 case 1:
585 // Continue with permissions check
586 break;
587 case 2:
588 panic("UNPRED domain\n");
589 case 3:
590 req->setPaddr(te->pAddr(vaddr));
591 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
592 if (fault)
593 return fault;
594 return NoFault;
595 }
596
597 uint8_t ap = te->ap;
598
599 if (sctlr.afe == 1)
600 ap |= 1;
601
602 bool abt;
603
604 /* if (!sctlr.xp)
605 ap &= 0x3;
606*/
607 switch (ap) {
608 case 0:
609 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
610 if (!sctlr.xp) {
611 switch ((int)sctlr.rs) {
612 case 2:
613 abt = is_write;
614 break;
615 case 1:
616 abt = is_write || !is_priv;
617 break;
618 case 0:
619 case 3:
620 default:
621 abt = true;
622 break;
623 }
624 } else {
625 abt = true;
626 }
627 break;
628 case 1:
629 abt = !is_priv;
630 break;
631 case 2:
632 abt = !is_priv && is_write;
633 break;
634 case 3:
635 abt = false;
636 break;
637 case 4:
638 panic("UNPRED premissions\n");
639 case 5:
640 abt = !is_priv || is_write;
641 break;
642 case 6:
643 case 7:
644 abt = is_write;
645 break;
646 default:
647 panic("Unknown permissions\n");
648 }
649 if ((is_fetch) && (abt || te->xn)) {
650 permsFaults++;
651 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
652 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
653 return new PrefetchAbort(vaddr,
654 (te->sNp ? ArmFault::Permission0 :
655 ArmFault::Permission1));
656 } else if (abt) {
657 permsFaults++;
658 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
659 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
660 return new DataAbort(vaddr, te->domain, is_write,
661 (te->sNp ? ArmFault::Permission0 :
662 ArmFault::Permission1));
663 }
664
665 req->setPaddr(te->pAddr(vaddr));
666 // Check for a trickbox generated address fault
667 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
668 if (fault)
669 return fault;
670
671 return NoFault;
672}
673
674#endif
675
676Fault
677TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
678{
679 bool delay = false;
680 Fault fault;
681#if FULL_SYSTEM
682 fault = translateFs(req, tc, mode, NULL, delay, false);
683#else
684 fault = translateSe(req, tc, mode, NULL, delay, false);
685#endif
686 assert(!delay);
687 return fault;
688}
689
690Fault
691TLB::translateTiming(RequestPtr req, ThreadContext *tc,
692 Translation *translation, Mode mode)
693{
694 assert(translation);
695 bool delay = false;
696 Fault fault;
697#if FULL_SYSTEM
698 fault = translateFs(req, tc, mode, translation, delay, true);
699#else
700 fault = translateSe(req, tc, mode, translation, delay, true);
701#endif
702 DPRINTF(TLB, "Translation returning delay=%d fault=%d\n", delay, fault !=
703 NoFault);
704 if (!delay)
705 translation->finish(fault, req, tc, mode);
706 else
707 translation->markDelayed();
708 return fault;
709}
710
711Port*
712TLB::getPort()
713{
714#if FULL_SYSTEM
715 return tableWalker->getPort("port");
716#else
717 return NULL;
718#endif
719}
720
721
722
723ArmISA::TLB *
724ArmTLBParams::create()
725{
726 return new ArmISA::TLB(this);
727}
196
197 flushTlb++;
198}
199
200
201void
202TLB::flushMvaAsid(Addr mva, uint64_t asn)
203{
204 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
205 TlbEntry *te;
206
207 te = lookup(mva, asn);
208 while (te != NULL) {
209 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
210 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
211 te->valid = false;
212 flushedEntries++;
213 te = lookup(mva,asn);
214 }
215 flushTlbMvaAsid++;
216}
217
218void
219TLB::flushAsid(uint64_t asn)
220{
221 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
222
223 int x = 0;
224 TlbEntry *te;
225
226 while (x < size) {
227 te = &table[x];
228 if (te->asid == asn) {
229 te->valid = false;
230 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
231 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
232 flushedEntries++;
233 }
234 x++;
235 }
236 flushTlbAsid++;
237}
238
239void
240TLB::flushMva(Addr mva)
241{
242 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
243
244 int x = 0;
245 TlbEntry *te;
246
247 while (x < size) {
248 te = &table[x];
249 Addr v = te->vpn << te->N;
250 if (mva >= v && mva < v + te->size) {
251 te->valid = false;
252 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
253 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
254 flushedEntries++;
255 }
256 x++;
257 }
258 flushTlbMva++;
259}
260
261void
262TLB::serialize(ostream &os)
263{
264 DPRINTF(Checkpoint, "Serializing Arm TLB\n");
265
266 SERIALIZE_SCALAR(_attr);
267 for(int i = 0; i < size; i++){
268 nameOut(os, csprintf("%s.TlbEntry%d", name(), i));
269 table[i].serialize(os);
270 }
271}
272
273void
274TLB::unserialize(Checkpoint *cp, const string &section)
275{
276 DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
277
278 UNSERIALIZE_SCALAR(_attr);
279 for(int i = 0; i < size; i++){
280 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
281 }
282 miscRegValid = false;
283}
284
285void
286TLB::regStats()
287{
288 instHits
289 .name(name() + ".inst_hits")
290 .desc("ITB inst hits")
291 ;
292
293 instMisses
294 .name(name() + ".inst_misses")
295 .desc("ITB inst misses")
296 ;
297
298 instAccesses
299 .name(name() + ".inst_accesses")
300 .desc("ITB inst accesses")
301 ;
302
303 readHits
304 .name(name() + ".read_hits")
305 .desc("DTB read hits")
306 ;
307
308 readMisses
309 .name(name() + ".read_misses")
310 .desc("DTB read misses")
311 ;
312
313 readAccesses
314 .name(name() + ".read_accesses")
315 .desc("DTB read accesses")
316 ;
317
318 writeHits
319 .name(name() + ".write_hits")
320 .desc("DTB write hits")
321 ;
322
323 writeMisses
324 .name(name() + ".write_misses")
325 .desc("DTB write misses")
326 ;
327
328 writeAccesses
329 .name(name() + ".write_accesses")
330 .desc("DTB write accesses")
331 ;
332
333 hits
334 .name(name() + ".hits")
335 .desc("DTB hits")
336 ;
337
338 misses
339 .name(name() + ".misses")
340 .desc("DTB misses")
341 ;
342
343 accesses
344 .name(name() + ".accesses")
345 .desc("DTB accesses")
346 ;
347
348 flushTlb
349 .name(name() + ".flush_tlb")
350 .desc("Number of times complete TLB was flushed")
351 ;
352
353 flushTlbMva
354 .name(name() + ".flush_tlb_mva")
355 .desc("Number of times TLB was flushed by MVA")
356 ;
357
358 flushTlbMvaAsid
359 .name(name() + ".flush_tlb_mva_asid")
360 .desc("Number of times TLB was flushed by MVA & ASID")
361 ;
362
363 flushTlbAsid
364 .name(name() + ".flush_tlb_asid")
365 .desc("Number of times TLB was flushed by ASID")
366 ;
367
368 flushedEntries
369 .name(name() + ".flush_entries")
370 .desc("Number of entries that have been flushed from TLB")
371 ;
372
373 alignFaults
374 .name(name() + ".align_faults")
375 .desc("Number of TLB faults due to alignment restrictions")
376 ;
377
378 prefetchFaults
379 .name(name() + ".prefetch_faults")
380 .desc("Number of TLB faults due to prefetch")
381 ;
382
383 domainFaults
384 .name(name() + ".domain_faults")
385 .desc("Number of TLB faults due to domain restrictions")
386 ;
387
388 permsFaults
389 .name(name() + ".perms_faults")
390 .desc("Number of TLB faults due to permissions restrictions")
391 ;
392
393 instAccesses = instHits + instMisses;
394 readAccesses = readHits + readMisses;
395 writeAccesses = writeHits + writeMisses;
396 hits = readHits + writeHits + instHits;
397 misses = readMisses + writeMisses + instMisses;
398 accesses = readAccesses + writeAccesses + instAccesses;
399}
400
401#if !FULL_SYSTEM
402Fault
403TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
404 Translation *translation, bool &delay, bool timing)
405{
406 if (!miscRegValid)
407 updateMiscReg(tc);
408 Addr vaddr = req->getVaddr();
409 uint32_t flags = req->getFlags();
410
411 bool is_fetch = (mode == Execute);
412 bool is_write = (mode == Write);
413
414 if (!is_fetch) {
415 assert(flags & MustBeOne);
416 if (sctlr.a || !(flags & AllowUnaligned)) {
417 if (vaddr & flags & AlignmentMask) {
418 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
419 }
420 }
421 }
422
423 Addr paddr;
424 Process *p = tc->getProcessPtr();
425
426 if (!p->pTable->translate(vaddr, paddr))
427 return Fault(new GenericPageTableFault(vaddr));
428 req->setPaddr(paddr);
429
430 return NoFault;
431}
432
433#else // FULL_SYSTEM
434
435Fault
436TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
437{
438 return NoFault;
439}
440
441Fault
442TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
443 bool is_write, uint8_t domain, bool sNp)
444{
445 return NoFault;
446}
447
448Fault
449TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
450 Translation *translation, bool &delay, bool timing)
451{
452 if (!miscRegValid) {
453 updateMiscReg(tc);
454 DPRINTF(TLBVerbose, "TLB variables changed!\n");
455 }
456
457 Addr vaddr = req->getVaddr();
458 uint32_t flags = req->getFlags();
459
460 bool is_fetch = (mode == Execute);
461 bool is_write = (mode == Write);
462 bool is_priv = isPriv && !(flags & UserMode);
463
464 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
465 isPriv, flags & UserMode);
466 // If this is a clrex instruction, provide a PA of 0 with no fault
467 // This will force the monitor to set the tracked address to 0
468 // a bit of a hack but this effectively clrears this processors monitor
469 if (flags & Request::CLEAR_LL){
470 req->setPaddr(0);
471 req->setFlags(Request::UNCACHEABLE);
472 req->setFlags(Request::CLEAR_LL);
473 return NoFault;
474 }
475 if ((req->isInstFetch() && (!sctlr.i)) ||
476 ((!req->isInstFetch()) && (!sctlr.c))){
477 req->setFlags(Request::UNCACHEABLE);
478 }
479 if (!is_fetch) {
480 assert(flags & MustBeOne);
481 if (sctlr.a || !(flags & AllowUnaligned)) {
482 if (vaddr & flags & AlignmentMask) {
483 alignFaults++;
484 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
485 }
486 }
487 }
488
489 Fault fault;
490
491 if (!sctlr.m) {
492 req->setPaddr(vaddr);
493 if (sctlr.tre == 0) {
494 req->setFlags(Request::UNCACHEABLE);
495 } else {
496 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
497 req->setFlags(Request::UNCACHEABLE);
498 }
499
500 // Set memory attributes
501 TlbEntry temp_te;
502 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
503 temp_te.shareable = true;
504 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
505 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
506 temp_te.innerAttrs, temp_te.outerAttrs);
507 setAttr(temp_te.attributes);
508
509 return trickBoxCheck(req, mode, 0, false);
510 }
511
512 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId);
513 // Translation enabled
514
515 TlbEntry *te = lookup(vaddr, contextId);
516 if (te == NULL) {
517 if (req->isPrefetch()){
518 //if the request is a prefetch don't attempt to fill the TLB
519 //or go any further with the memory access
520 prefetchFaults++;
521 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
522 }
523
524 if (is_fetch)
525 instMisses++;
526 else if (is_write)
527 writeMisses++;
528 else
529 readMisses++;
530
531 // start translation table walk, pass variables rather than
532 // re-retreaving in table walker for speed
533 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
534 vaddr, contextId);
535 fault = tableWalker->walk(req, tc, contextId, mode, translation,
536 timing);
537 if (timing && fault == NoFault) {
538 delay = true;
539 // for timing mode, return and wait for table walk
540 return fault;
541 }
542 if (fault)
543 return fault;
544
545 te = lookup(vaddr, contextId);
546 if (!te)
547 printTlb();
548 assert(te);
549 } else {
550 if (is_fetch)
551 instHits++;
552 else if (is_write)
553 writeHits++;
554 else
555 readHits++;
556 }
557
558 // Set memory attributes
559 DPRINTF(TLBVerbose,
560 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
561 outerAttrs: %d\n",
562 te->shareable, te->innerAttrs, te->outerAttrs);
563 setAttr(te->attributes);
564 if (te->nonCacheable) {
565 req->setFlags(Request::UNCACHEABLE);
566
567 // Prevent prefetching from I/O devices.
568 if (req->isPrefetch()) {
569 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
570 }
571 }
572
573 switch ( (dacr >> (te->domain * 2)) & 0x3) {
574 case 0:
575 domainFaults++;
576 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
577 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
578 if (is_fetch)
579 return new PrefetchAbort(vaddr,
580 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
581 else
582 return new DataAbort(vaddr, te->domain, is_write,
583 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
584 case 1:
585 // Continue with permissions check
586 break;
587 case 2:
588 panic("UNPRED domain\n");
589 case 3:
590 req->setPaddr(te->pAddr(vaddr));
591 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
592 if (fault)
593 return fault;
594 return NoFault;
595 }
596
597 uint8_t ap = te->ap;
598
599 if (sctlr.afe == 1)
600 ap |= 1;
601
602 bool abt;
603
604 /* if (!sctlr.xp)
605 ap &= 0x3;
606*/
607 switch (ap) {
608 case 0:
609 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
610 if (!sctlr.xp) {
611 switch ((int)sctlr.rs) {
612 case 2:
613 abt = is_write;
614 break;
615 case 1:
616 abt = is_write || !is_priv;
617 break;
618 case 0:
619 case 3:
620 default:
621 abt = true;
622 break;
623 }
624 } else {
625 abt = true;
626 }
627 break;
628 case 1:
629 abt = !is_priv;
630 break;
631 case 2:
632 abt = !is_priv && is_write;
633 break;
634 case 3:
635 abt = false;
636 break;
637 case 4:
638 panic("UNPRED premissions\n");
639 case 5:
640 abt = !is_priv || is_write;
641 break;
642 case 6:
643 case 7:
644 abt = is_write;
645 break;
646 default:
647 panic("Unknown permissions\n");
648 }
649 if ((is_fetch) && (abt || te->xn)) {
650 permsFaults++;
651 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
652 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
653 return new PrefetchAbort(vaddr,
654 (te->sNp ? ArmFault::Permission0 :
655 ArmFault::Permission1));
656 } else if (abt) {
657 permsFaults++;
658 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
659 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
660 return new DataAbort(vaddr, te->domain, is_write,
661 (te->sNp ? ArmFault::Permission0 :
662 ArmFault::Permission1));
663 }
664
665 req->setPaddr(te->pAddr(vaddr));
666 // Check for a trickbox generated address fault
667 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
668 if (fault)
669 return fault;
670
671 return NoFault;
672}
673
674#endif
675
676Fault
677TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
678{
679 bool delay = false;
680 Fault fault;
681#if FULL_SYSTEM
682 fault = translateFs(req, tc, mode, NULL, delay, false);
683#else
684 fault = translateSe(req, tc, mode, NULL, delay, false);
685#endif
686 assert(!delay);
687 return fault;
688}
689
690Fault
691TLB::translateTiming(RequestPtr req, ThreadContext *tc,
692 Translation *translation, Mode mode)
693{
694 assert(translation);
695 bool delay = false;
696 Fault fault;
697#if FULL_SYSTEM
698 fault = translateFs(req, tc, mode, translation, delay, true);
699#else
700 fault = translateSe(req, tc, mode, translation, delay, true);
701#endif
702 DPRINTF(TLB, "Translation returning delay=%d fault=%d\n", delay, fault !=
703 NoFault);
704 if (!delay)
705 translation->finish(fault, req, tc, mode);
706 else
707 translation->markDelayed();
708 return fault;
709}
710
711Port*
712TLB::getPort()
713{
714#if FULL_SYSTEM
715 return tableWalker->getPort("port");
716#else
717 return NULL;
718#endif
719}
720
721
722
723ArmISA::TLB *
724ArmTLBParams::create()
725{
726 return new ArmISA::TLB(this);
727}