1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" 50#include "arch/arm/tlb.hh" 51#include "arch/arm/utility.hh" 52#include "base/inifile.hh" 53#include "base/str.hh" 54#include "base/trace.hh" 55#include "cpu/thread_context.hh" 56#include "mem/page_table.hh" 57#include "params/ArmTLB.hh" 58#include "sim/process.hh" 59 60#if FULL_SYSTEM 61#include "arch/arm/table_walker.hh" 62#endif 63 64using namespace std; 65using namespace ArmISA; 66 67TLB::TLB(const Params *p) 68 : BaseTLB(p), size(p->size) 69#if FULL_SYSTEM 70 , tableWalker(p->walker) 71#endif 72 , rangeMRU(1) 73{ 74 table = new TlbEntry[size]; 75 memset(table, 0, sizeof(TlbEntry[size])); 76 77#if FULL_SYSTEM 78 tableWalker->setTlb(this); 79#endif 80} 81 82TLB::~TLB() 83{ 84 if (table) 85 delete [] table; 86} 87 88bool 89TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 90{ 91 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 92 TlbEntry *e = lookup(va, context_id, true); 93 if (!e) 94 return false; 95 pa = e->pAddr(va); 96 return true; 97} 98 99TlbEntry* 100TLB::lookup(Addr va, uint8_t cid, bool functional) 101{ 102 103 TlbEntry *retval = NULL; 104 105 // Maitaining LRU array 106 107 int x = 0; 108 while (retval == NULL && x < size) { 109 if (table[x].match(va, cid)) { 110 111 // We only move the hit entry ahead when the position is higher than rangeMRU 112 if (x > rangeMRU) { 113 TlbEntry tmp_entry = table[x]; 114 for(int i = x; i > 0; i--) 115 table[i] = table[i-1]; 116 table[0] = tmp_entry; 117 retval = &table[0]; 118 } else { 119 retval = &table[x]; 120 } 121 break; 122 } 123 x++; 124 } 125 126 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 127 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 128 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 129 retval ? retval->ap : 0); 130 ; 131 return retval; 132} 133 134// insert a new TLB entry 135void 136TLB::insert(Addr addr, TlbEntry &entry) 137{ 138 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 139 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 140 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 141 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 142 entry.xn, entry.ap, entry.domain); 143 144 if (table[size-1].valid) 145 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 146 table[size-1].vpn << table[size-1].N, table[size-1].asid, 147 table[size-1].pfn << table[size-1].N, table[size-1].size, 148 table[size-1].ap); 149 150 //inserting to MRU position and evicting the LRU one 151 152 for(int i = size-1; i > 0; i--) 153 table[i] = table[i-1]; 154 table[0] = entry;
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" 50#include "arch/arm/tlb.hh" 51#include "arch/arm/utility.hh" 52#include "base/inifile.hh" 53#include "base/str.hh" 54#include "base/trace.hh" 55#include "cpu/thread_context.hh" 56#include "mem/page_table.hh" 57#include "params/ArmTLB.hh" 58#include "sim/process.hh" 59 60#if FULL_SYSTEM 61#include "arch/arm/table_walker.hh" 62#endif 63 64using namespace std; 65using namespace ArmISA; 66 67TLB::TLB(const Params *p) 68 : BaseTLB(p), size(p->size) 69#if FULL_SYSTEM 70 , tableWalker(p->walker) 71#endif 72 , rangeMRU(1) 73{ 74 table = new TlbEntry[size]; 75 memset(table, 0, sizeof(TlbEntry[size])); 76 77#if FULL_SYSTEM 78 tableWalker->setTlb(this); 79#endif 80} 81 82TLB::~TLB() 83{ 84 if (table) 85 delete [] table; 86} 87 88bool 89TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 90{ 91 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 92 TlbEntry *e = lookup(va, context_id, true); 93 if (!e) 94 return false; 95 pa = e->pAddr(va); 96 return true; 97} 98 99TlbEntry* 100TLB::lookup(Addr va, uint8_t cid, bool functional) 101{ 102 103 TlbEntry *retval = NULL; 104 105 // Maitaining LRU array 106 107 int x = 0; 108 while (retval == NULL && x < size) { 109 if (table[x].match(va, cid)) { 110 111 // We only move the hit entry ahead when the position is higher than rangeMRU 112 if (x > rangeMRU) { 113 TlbEntry tmp_entry = table[x]; 114 for(int i = x; i > 0; i--) 115 table[i] = table[i-1]; 116 table[0] = tmp_entry; 117 retval = &table[0]; 118 } else { 119 retval = &table[x]; 120 } 121 break; 122 } 123 x++; 124 } 125 126 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 127 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 128 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 129 retval ? retval->ap : 0); 130 ; 131 return retval; 132} 133 134// insert a new TLB entry 135void 136TLB::insert(Addr addr, TlbEntry &entry) 137{ 138 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 139 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 140 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 141 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 142 entry.xn, entry.ap, entry.domain); 143 144 if (table[size-1].valid) 145 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 146 table[size-1].vpn << table[size-1].N, table[size-1].asid, 147 table[size-1].pfn << table[size-1].N, table[size-1].size, 148 table[size-1].ap); 149 150 //inserting to MRU position and evicting the LRU one 151 152 for(int i = size-1; i > 0; i--) 153 table[i] = table[i-1]; 154 table[0] = entry;
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| 155 156 inserts++;
|
155} 156 157void 158TLB::printTlb() 159{ 160 int x = 0; 161 TlbEntry *te; 162 DPRINTF(TLB, "Current TLB contents:\n"); 163 while (x < size) { 164 te = &table[x]; 165 if (te->valid) 166 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 167 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 168 x++; 169 } 170} 171 172 173void 174TLB::flushAll() 175{ 176 DPRINTF(TLB, "Flushing all TLB entries\n"); 177 int x = 0; 178 TlbEntry *te; 179 while (x < size) { 180 te = &table[x];
| 157} 158 159void 160TLB::printTlb() 161{ 162 int x = 0; 163 TlbEntry *te; 164 DPRINTF(TLB, "Current TLB contents:\n"); 165 while (x < size) { 166 te = &table[x]; 167 if (te->valid) 168 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 169 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 170 x++; 171 } 172} 173 174 175void 176TLB::flushAll() 177{ 178 DPRINTF(TLB, "Flushing all TLB entries\n"); 179 int x = 0; 180 TlbEntry *te; 181 while (x < size) { 182 te = &table[x];
|
181 if (te->valid)
| 183 if (te->valid) {
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182 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 183 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
| 184 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 185 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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| 186 flushedEntries++; 187 }
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184 x++; 185 } 186 187 memset(table, 0, sizeof(TlbEntry[size]));
| 188 x++; 189 } 190 191 memset(table, 0, sizeof(TlbEntry[size]));
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| 192 193 flushTlb++;
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188} 189 190 191void 192TLB::flushMvaAsid(Addr mva, uint64_t asn) 193{ 194 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 195 TlbEntry *te; 196 197 te = lookup(mva, asn); 198 while (te != NULL) { 199 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 200 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 201 te->valid = false;
| 194} 195 196 197void 198TLB::flushMvaAsid(Addr mva, uint64_t asn) 199{ 200 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 201 TlbEntry *te; 202 203 te = lookup(mva, asn); 204 while (te != NULL) { 205 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 206 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 207 te->valid = false;
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| 208 flushedEntries++;
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202 te = lookup(mva,asn); 203 }
| 209 te = lookup(mva,asn); 210 }
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| 211 flushTlbMvaAsid++;
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204} 205 206void 207TLB::flushAsid(uint64_t asn) 208{ 209 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 210 211 int x = 0; 212 TlbEntry *te; 213 214 while (x < size) { 215 te = &table[x]; 216 if (te->asid == asn) { 217 te->valid = false; 218 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 219 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
| 212} 213 214void 215TLB::flushAsid(uint64_t asn) 216{ 217 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 218 219 int x = 0; 220 TlbEntry *te; 221 222 while (x < size) { 223 te = &table[x]; 224 if (te->asid == asn) { 225 te->valid = false; 226 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 227 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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| 228 flushedEntries++;
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220 } 221 x++; 222 }
| 229 } 230 x++; 231 }
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| 232 flushTlbAsid++;
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223} 224 225void 226TLB::flushMva(Addr mva) 227{ 228 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 229 230 int x = 0; 231 TlbEntry *te; 232 233 while (x < size) { 234 te = &table[x]; 235 Addr v = te->vpn << te->N; 236 if (mva >= v && mva < v + te->size) { 237 te->valid = false; 238 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 239 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
| 233} 234 235void 236TLB::flushMva(Addr mva) 237{ 238 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 239 240 int x = 0; 241 TlbEntry *te; 242 243 while (x < size) { 244 te = &table[x]; 245 Addr v = te->vpn << te->N; 246 if (mva >= v && mva < v + te->size) { 247 te->valid = false; 248 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 249 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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| 250 flushedEntries++;
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240 } 241 x++; 242 }
| 251 } 252 x++; 253 }
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| 254 flushTlbMva++;
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243} 244 245void 246TLB::serialize(ostream &os) 247{ 248 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 249 250 SERIALIZE_SCALAR(_attr); 251 for(int i = 0; i < size; i++){ 252 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 253 table[i].serialize(os); 254 } 255} 256 257void 258TLB::unserialize(Checkpoint *cp, const string §ion) 259{ 260 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 261 262 UNSERIALIZE_SCALAR(_attr); 263 for(int i = 0; i < size; i++){ 264 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 265 } 266} 267 268void 269TLB::regStats() 270{
| 255} 256 257void 258TLB::serialize(ostream &os) 259{ 260 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 261 262 SERIALIZE_SCALAR(_attr); 263 for(int i = 0; i < size; i++){ 264 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 265 table[i].serialize(os); 266 } 267} 268 269void 270TLB::unserialize(Checkpoint *cp, const string §ion) 271{ 272 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 273 274 UNSERIALIZE_SCALAR(_attr); 275 for(int i = 0; i < size; i++){ 276 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 277 } 278} 279 280void 281TLB::regStats() 282{
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271 read_hits
| 283 instHits 284 .name(name() + ".inst_hits") 285 .desc("ITB inst hits") 286 ; 287 288 instMisses 289 .name(name() + ".inst_misses") 290 .desc("ITB inst misses") 291 ; 292 293 instAccesses 294 .name(name() + ".inst_accesses") 295 .desc("ITB inst accesses") 296 ; 297 298 readHits
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272 .name(name() + ".read_hits") 273 .desc("DTB read hits") 274 ; 275
| 299 .name(name() + ".read_hits") 300 .desc("DTB read hits") 301 ; 302
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276 read_misses
| 303 readMisses
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277 .name(name() + ".read_misses") 278 .desc("DTB read misses") 279 ; 280
| 304 .name(name() + ".read_misses") 305 .desc("DTB read misses") 306 ; 307
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281 282 read_accesses
| 308 readAccesses
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283 .name(name() + ".read_accesses") 284 .desc("DTB read accesses") 285 ; 286
| 309 .name(name() + ".read_accesses") 310 .desc("DTB read accesses") 311 ; 312
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287 write_hits
| 313 writeHits
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288 .name(name() + ".write_hits") 289 .desc("DTB write hits") 290 ; 291
| 314 .name(name() + ".write_hits") 315 .desc("DTB write hits") 316 ; 317
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292 write_misses
| 318 writeMisses
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293 .name(name() + ".write_misses") 294 .desc("DTB write misses") 295 ; 296
| 319 .name(name() + ".write_misses") 320 .desc("DTB write misses") 321 ; 322
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297 298 write_accesses
| 323 writeAccesses
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299 .name(name() + ".write_accesses") 300 .desc("DTB write accesses") 301 ; 302 303 hits 304 .name(name() + ".hits") 305 .desc("DTB hits") 306 ; 307 308 misses 309 .name(name() + ".misses") 310 .desc("DTB misses") 311 ; 312 313 accesses 314 .name(name() + ".accesses") 315 .desc("DTB accesses") 316 ; 317
| 324 .name(name() + ".write_accesses") 325 .desc("DTB write accesses") 326 ; 327 328 hits 329 .name(name() + ".hits") 330 .desc("DTB hits") 331 ; 332 333 misses 334 .name(name() + ".misses") 335 .desc("DTB misses") 336 ; 337 338 accesses 339 .name(name() + ".accesses") 340 .desc("DTB accesses") 341 ; 342
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318 hits = read_hits + write_hits; 319 misses = read_misses + write_misses; 320 accesses = read_accesses + write_accesses;
| 343 flushTlb 344 .name(name() + ".flush_tlb") 345 .desc("Number of times complete TLB was flushed") 346 ; 347 348 flushTlbMva 349 .name(name() + ".flush_tlb_mva") 350 .desc("Number of times TLB was flushed by MVA") 351 ; 352 353 flushTlbMvaAsid 354 .name(name() + ".flush_tlb_mva_asid") 355 .desc("Number of times TLB was flushed by MVA & ASID") 356 ; 357 358 flushTlbAsid 359 .name(name() + ".flush_tlb_asid") 360 .desc("Number of times TLB was flushed by ASID") 361 ; 362 363 flushedEntries 364 .name(name() + ".flush_entries") 365 .desc("Number of entries that have been flushed from TLB") 366 ; 367 368 alignFaults 369 .name(name() + ".align_faults") 370 .desc("Number of TLB faults due to alignment restrictions") 371 ; 372 373 prefetchFaults 374 .name(name() + ".prefetch_faults") 375 .desc("Number of TLB faults due to prefetch") 376 ; 377 378 domainFaults 379 .name(name() + ".domain_faults") 380 .desc("Number of TLB faults due to domain restrictions") 381 ; 382 383 permsFaults 384 .name(name() + ".perms_faults") 385 .desc("Number of TLB faults due to permissions restrictions") 386 ; 387 388 instAccesses = instHits + instMisses; 389 readAccesses = readHits + readMisses; 390 writeAccesses = writeHits + writeMisses; 391 hits = readHits + writeHits + instHits; 392 misses = readMisses + writeMisses + instMisses; 393 accesses = readAccesses + writeAccesses + instAccesses;
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321} 322 323#if !FULL_SYSTEM 324Fault 325TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 326 Translation *translation, bool &delay, bool timing) 327{ 328 // XXX Cache misc registers and have miscreg write function inv cache 329 Addr vaddr = req->getVaddr(); 330 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 331 uint32_t flags = req->getFlags(); 332 333 bool is_fetch = (mode == Execute); 334 bool is_write = (mode == Write); 335 336 if (!is_fetch) { 337 assert(flags & MustBeOne); 338 if (sctlr.a || !(flags & AllowUnaligned)) { 339 if (vaddr & flags & AlignmentMask) { 340 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 341 } 342 } 343 } 344 345 Addr paddr; 346 Process *p = tc->getProcessPtr(); 347 348 if (!p->pTable->translate(vaddr, paddr)) 349 return Fault(new GenericPageTableFault(vaddr)); 350 req->setPaddr(paddr); 351 352 return NoFault; 353} 354 355#else // FULL_SYSTEM 356 357Fault 358TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 359{ 360 return NoFault; 361} 362 363Fault 364TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 365 bool is_write, uint8_t domain, bool sNp) 366{ 367 return NoFault; 368} 369 370Fault 371TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 372 Translation *translation, bool &delay, bool timing) 373{ 374 // XXX Cache misc registers and have miscreg write function inv cache 375 Addr vaddr = req->getVaddr(); 376 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 377 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 378 uint32_t flags = req->getFlags(); 379 380 bool is_fetch = (mode == Execute); 381 bool is_write = (mode == Write); 382 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 383 384 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 385 & UserMode); 386 // If this is a clrex instruction, provide a PA of 0 with no fault 387 // This will force the monitor to set the tracked address to 0 388 // a bit of a hack but this effectively clrears this processors monitor 389 if (flags & Request::CLEAR_LL){ 390 req->setPaddr(0); 391 req->setFlags(Request::UNCACHEABLE); 392 req->setFlags(Request::CLEAR_LL); 393 return NoFault; 394 } 395 if ((req->isInstFetch() && (!sctlr.i)) || 396 ((!req->isInstFetch()) && (!sctlr.c))){ 397 req->setFlags(Request::UNCACHEABLE); 398 } 399 if (!is_fetch) { 400 assert(flags & MustBeOne); 401 if (sctlr.a || !(flags & AllowUnaligned)) { 402 if (vaddr & flags & AlignmentMask) {
| 394} 395 396#if !FULL_SYSTEM 397Fault 398TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 399 Translation *translation, bool &delay, bool timing) 400{ 401 // XXX Cache misc registers and have miscreg write function inv cache 402 Addr vaddr = req->getVaddr(); 403 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 404 uint32_t flags = req->getFlags(); 405 406 bool is_fetch = (mode == Execute); 407 bool is_write = (mode == Write); 408 409 if (!is_fetch) { 410 assert(flags & MustBeOne); 411 if (sctlr.a || !(flags & AllowUnaligned)) { 412 if (vaddr & flags & AlignmentMask) { 413 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 414 } 415 } 416 } 417 418 Addr paddr; 419 Process *p = tc->getProcessPtr(); 420 421 if (!p->pTable->translate(vaddr, paddr)) 422 return Fault(new GenericPageTableFault(vaddr)); 423 req->setPaddr(paddr); 424 425 return NoFault; 426} 427 428#else // FULL_SYSTEM 429 430Fault 431TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 432{ 433 return NoFault; 434} 435 436Fault 437TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 438 bool is_write, uint8_t domain, bool sNp) 439{ 440 return NoFault; 441} 442 443Fault 444TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 445 Translation *translation, bool &delay, bool timing) 446{ 447 // XXX Cache misc registers and have miscreg write function inv cache 448 Addr vaddr = req->getVaddr(); 449 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 450 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 451 uint32_t flags = req->getFlags(); 452 453 bool is_fetch = (mode == Execute); 454 bool is_write = (mode == Write); 455 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 456 457 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 458 & UserMode); 459 // If this is a clrex instruction, provide a PA of 0 with no fault 460 // This will force the monitor to set the tracked address to 0 461 // a bit of a hack but this effectively clrears this processors monitor 462 if (flags & Request::CLEAR_LL){ 463 req->setPaddr(0); 464 req->setFlags(Request::UNCACHEABLE); 465 req->setFlags(Request::CLEAR_LL); 466 return NoFault; 467 } 468 if ((req->isInstFetch() && (!sctlr.i)) || 469 ((!req->isInstFetch()) && (!sctlr.c))){ 470 req->setFlags(Request::UNCACHEABLE); 471 } 472 if (!is_fetch) { 473 assert(flags & MustBeOne); 474 if (sctlr.a || !(flags & AllowUnaligned)) { 475 if (vaddr & flags & AlignmentMask) {
|
| 476 alignFaults++;
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403 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 404 } 405 } 406 } 407 408 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 409 Fault fault; 410 411 412 if (!sctlr.m) { 413 req->setPaddr(vaddr); 414 if (sctlr.tre == 0) { 415 req->setFlags(Request::UNCACHEABLE); 416 } else { 417 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 418 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 419 420 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 421 req->setFlags(Request::UNCACHEABLE); 422 } 423 424 // Set memory attributes 425 TlbEntry temp_te; 426 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 427 temp_te.shareable = true; 428 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 429 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 430 temp_te.innerAttrs, temp_te.outerAttrs); 431 setAttr(temp_te.attributes); 432 433 return trickBoxCheck(req, mode, 0, false); 434 } 435 436 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 437 // Translation enabled 438 439 TlbEntry *te = lookup(vaddr, context_id); 440 if (te == NULL) { 441 if (req->isPrefetch()){ 442 //if the request is a prefetch don't attempt to fill the TLB 443 //or go any further with the memory access
| 477 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 478 } 479 } 480 } 481 482 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 483 Fault fault; 484 485 486 if (!sctlr.m) { 487 req->setPaddr(vaddr); 488 if (sctlr.tre == 0) { 489 req->setFlags(Request::UNCACHEABLE); 490 } else { 491 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 492 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 493 494 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 495 req->setFlags(Request::UNCACHEABLE); 496 } 497 498 // Set memory attributes 499 TlbEntry temp_te; 500 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 501 temp_te.shareable = true; 502 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 503 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 504 temp_te.innerAttrs, temp_te.outerAttrs); 505 setAttr(temp_te.attributes); 506 507 return trickBoxCheck(req, mode, 0, false); 508 } 509 510 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 511 // Translation enabled 512 513 TlbEntry *te = lookup(vaddr, context_id); 514 if (te == NULL) { 515 if (req->isPrefetch()){ 516 //if the request is a prefetch don't attempt to fill the TLB 517 //or go any further with the memory access
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| 518 prefetchFaults++;
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444 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 445 }
| 519 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 520 }
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| 521 522 if (is_fetch) 523 instMisses++; 524 else if (is_write) 525 writeMisses++; 526 else 527 readMisses++; 528
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446 // start translation table walk, pass variables rather than 447 // re-retreaving in table walker for speed 448 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 449 vaddr, context_id); 450 fault = tableWalker->walk(req, tc, context_id, mode, translation, 451 timing); 452 if (timing) { 453 delay = true; 454 // for timing mode, return and wait for table walk 455 return fault; 456 } 457 if (fault) 458 return fault; 459 460 te = lookup(vaddr, context_id); 461 if (!te) 462 printTlb(); 463 assert(te);
| 529 // start translation table walk, pass variables rather than 530 // re-retreaving in table walker for speed 531 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 532 vaddr, context_id); 533 fault = tableWalker->walk(req, tc, context_id, mode, translation, 534 timing); 535 if (timing) { 536 delay = true; 537 // for timing mode, return and wait for table walk 538 return fault; 539 } 540 if (fault) 541 return fault; 542 543 te = lookup(vaddr, context_id); 544 if (!te) 545 printTlb(); 546 assert(te);
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| 547 } else { 548 if (is_fetch) 549 instHits++; 550 else if (is_write) 551 writeHits++; 552 else 553 readHits++;
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464 } 465 466 // Set memory attributes 467 DPRINTF(TLBVerbose, 468 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 469 outerAttrs: %d\n", 470 te->shareable, te->innerAttrs, te->outerAttrs); 471 setAttr(te->attributes); 472 if (te->nonCacheable) 473 req->setFlags(Request::UNCACHEABLE); 474 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 475 switch ( (dacr >> (te->domain * 2)) & 0x3) { 476 case 0:
| 554 } 555 556 // Set memory attributes 557 DPRINTF(TLBVerbose, 558 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 559 outerAttrs: %d\n", 560 te->shareable, te->innerAttrs, te->outerAttrs); 561 setAttr(te->attributes); 562 if (te->nonCacheable) 563 req->setFlags(Request::UNCACHEABLE); 564 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 565 switch ( (dacr >> (te->domain * 2)) & 0x3) { 566 case 0:
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| 567 domainFaults++;
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477 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 478 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 479 if (is_fetch) 480 return new PrefetchAbort(vaddr, 481 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 482 else 483 return new DataAbort(vaddr, te->domain, is_write, 484 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 485 case 1: 486 // Continue with permissions check 487 break; 488 case 2: 489 panic("UNPRED domain\n"); 490 case 3: 491 req->setPaddr(te->pAddr(vaddr)); 492 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 493 if (fault) 494 return fault; 495 return NoFault; 496 } 497 498 uint8_t ap = te->ap; 499 500 if (sctlr.afe == 1) 501 ap |= 1; 502 503 bool abt; 504 505 /* if (!sctlr.xp) 506 ap &= 0x3; 507*/ 508 switch (ap) { 509 case 0: 510 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 511 if (!sctlr.xp) { 512 switch ((int)sctlr.rs) { 513 case 2: 514 abt = is_write; 515 break; 516 case 1: 517 abt = is_write || !is_priv; 518 break; 519 case 0: 520 case 3: 521 default: 522 abt = true; 523 break; 524 } 525 } else { 526 abt = true; 527 } 528 break; 529 case 1: 530 abt = !is_priv; 531 break; 532 case 2: 533 abt = !is_priv && is_write; 534 break; 535 case 3: 536 abt = false; 537 break; 538 case 4: 539 panic("UNPRED premissions\n"); 540 case 5: 541 abt = !is_priv || is_write; 542 break; 543 case 6: 544 case 7: 545 abt = is_write; 546 break; 547 default: 548 panic("Unknown permissions\n"); 549 } 550 if ((is_fetch) && (abt || te->xn)) {
| 568 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 569 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 570 if (is_fetch) 571 return new PrefetchAbort(vaddr, 572 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 573 else 574 return new DataAbort(vaddr, te->domain, is_write, 575 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 576 case 1: 577 // Continue with permissions check 578 break; 579 case 2: 580 panic("UNPRED domain\n"); 581 case 3: 582 req->setPaddr(te->pAddr(vaddr)); 583 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 584 if (fault) 585 return fault; 586 return NoFault; 587 } 588 589 uint8_t ap = te->ap; 590 591 if (sctlr.afe == 1) 592 ap |= 1; 593 594 bool abt; 595 596 /* if (!sctlr.xp) 597 ap &= 0x3; 598*/ 599 switch (ap) { 600 case 0: 601 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 602 if (!sctlr.xp) { 603 switch ((int)sctlr.rs) { 604 case 2: 605 abt = is_write; 606 break; 607 case 1: 608 abt = is_write || !is_priv; 609 break; 610 case 0: 611 case 3: 612 default: 613 abt = true; 614 break; 615 } 616 } else { 617 abt = true; 618 } 619 break; 620 case 1: 621 abt = !is_priv; 622 break; 623 case 2: 624 abt = !is_priv && is_write; 625 break; 626 case 3: 627 abt = false; 628 break; 629 case 4: 630 panic("UNPRED premissions\n"); 631 case 5: 632 abt = !is_priv || is_write; 633 break; 634 case 6: 635 case 7: 636 abt = is_write; 637 break; 638 default: 639 panic("Unknown permissions\n"); 640 } 641 if ((is_fetch) && (abt || te->xn)) {
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| 642 permsFaults++;
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551 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 552 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 553 return new PrefetchAbort(vaddr, 554 (te->sNp ? ArmFault::Permission0 : 555 ArmFault::Permission1)); 556 } else if (abt) {
| 643 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 644 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 645 return new PrefetchAbort(vaddr, 646 (te->sNp ? ArmFault::Permission0 : 647 ArmFault::Permission1)); 648 } else if (abt) {
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| 649 permsFaults++;
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557 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 558 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 559 return new DataAbort(vaddr, te->domain, is_write, 560 (te->sNp ? ArmFault::Permission0 : 561 ArmFault::Permission1)); 562 } 563 564 req->setPaddr(te->pAddr(vaddr)); 565 // Check for a trickbox generated address fault 566 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 567 if (fault) 568 return fault; 569 570 return NoFault; 571} 572 573#endif 574 575Fault 576TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 577{ 578 bool delay = false; 579 Fault fault; 580#if FULL_SYSTEM 581 fault = translateFs(req, tc, mode, NULL, delay, false); 582#else 583 fault = translateSe(req, tc, mode, NULL, delay, false); 584#endif 585 assert(!delay); 586 return fault; 587} 588 589Fault 590TLB::translateTiming(RequestPtr req, ThreadContext *tc, 591 Translation *translation, Mode mode) 592{ 593 assert(translation); 594 bool delay = false; 595 Fault fault; 596#if FULL_SYSTEM 597 fault = translateFs(req, tc, mode, translation, delay, true); 598#else 599 fault = translateSe(req, tc, mode, translation, delay, true); 600#endif 601 if (!delay) 602 translation->finish(fault, req, tc, mode); 603 return fault; 604} 605 606ArmISA::TLB * 607ArmTLBParams::create() 608{ 609 return new ArmISA::TLB(this); 610}
| 650 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 651 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 652 return new DataAbort(vaddr, te->domain, is_write, 653 (te->sNp ? ArmFault::Permission0 : 654 ArmFault::Permission1)); 655 } 656 657 req->setPaddr(te->pAddr(vaddr)); 658 // Check for a trickbox generated address fault 659 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 660 if (fault) 661 return fault; 662 663 return NoFault; 664} 665 666#endif 667 668Fault 669TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 670{ 671 bool delay = false; 672 Fault fault; 673#if FULL_SYSTEM 674 fault = translateFs(req, tc, mode, NULL, delay, false); 675#else 676 fault = translateSe(req, tc, mode, NULL, delay, false); 677#endif 678 assert(!delay); 679 return fault; 680} 681 682Fault 683TLB::translateTiming(RequestPtr req, ThreadContext *tc, 684 Translation *translation, Mode mode) 685{ 686 assert(translation); 687 bool delay = false; 688 Fault fault; 689#if FULL_SYSTEM 690 fault = translateFs(req, tc, mode, translation, delay, true); 691#else 692 fault = translateSe(req, tc, mode, translation, delay, true); 693#endif 694 if (!delay) 695 translation->finish(fault, req, tc, mode); 696 return fault; 697} 698 699ArmISA::TLB * 700ArmTLBParams::create() 701{ 702 return new ArmISA::TLB(this); 703}
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