1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "mem/page_table.hh"
57#include "params/ArmTLB.hh"
58#include "sim/process.hh"
59
60#if FULL_SYSTEM
61#include "arch/arm/table_walker.hh"
62#endif
63
64using namespace std;
65using namespace ArmISA;
66
67TLB::TLB(const Params *p)
68 : BaseTLB(p), size(p->size), nlu(0)
69#if FULL_SYSTEM
70 , tableWalker(p->walker)
71#endif
72{
73 table = new TlbEntry[size];
74 memset(table, 0, sizeof(TlbEntry[size]));
75
76#if FULL_SYSTEM
77 tableWalker->setTlb(this);
78#endif
79}
80
81TLB::~TLB()
82{
83 if (table)
84 delete [] table;
85}
86
87TlbEntry*
88TLB::lookup(Addr va, uint8_t cid)
89{
90 // XXX This should either turn into a TlbMap or add caching
91
92 TlbEntry *retval = NULL;
93
94 // Do some kind of caching, fast indexing, anything
95
96 int x = 0;
97 while (retval == NULL && x < size) {
98 if (table[x].match(va, cid)) {
99 retval = &table[x];
100 if (x == nlu)
101 nextnlu();
102
103 break;
104 }
105 x++;
106 }
107
108 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
109 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
110 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
111 retval ? retval->ap : 0);
112 ;
113 return retval;
114}
115
116// insert a new TLB entry
117void
118TLB::insert(Addr addr, TlbEntry &entry)
119{
120 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
121 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
122 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
123 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
124 entry.xn, entry.ap, entry.domain);
125
126 if (table[nlu].valid)
127 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
128 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N,
129 table[nlu].size, table[nlu].ap);
130
131 // XXX Update caching, lookup table etc
132 table[nlu] = entry;
133
134 // XXX Figure out how entries are generally inserted in ARM
135 nextnlu();
136}
137
138void
139TLB::printTlb()
140{
141 int x = 0;
142 TlbEntry *te;
143 DPRINTF(TLB, "Current TLB contents:\n");
144 while (x < size) {
145 te = &table[x];
146 if (te->valid)
147 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
148 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
149 x++;
150 }
151}
152
153
154void
155TLB::flushAll()
156{
157 DPRINTF(TLB, "Flushing all TLB entries\n");
158 int x = 0;
159 TlbEntry *te;
160 while (x < size) {
161 te = &table[x];
162 if (te->valid)
163 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
164 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
165 x++;
166 }
167
168 memset(table, 0, sizeof(TlbEntry[size]));
169 nlu = 0;
170}
171
172
173void
174TLB::flushMvaAsid(Addr mva, uint64_t asn)
175{
176 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
177 TlbEntry *te;
178
179 te = lookup(mva, asn);
180 while (te != NULL) {
181 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
182 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
183 te->valid = false;
184 te = lookup(mva,asn);
185 }
186}
187
188void
189TLB::flushAsid(uint64_t asn)
190{
191 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
192
193 int x = 0;
194 TlbEntry *te;
195
196 while (x < size) {
197 te = &table[x];
198 if (te->asid == asn) {
199 te->valid = false;
200 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
201 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
202 }
203 x++;
204 }
205}
206
207void
208TLB::flushMva(Addr mva)
209{
210 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
211
212 int x = 0;
213 TlbEntry *te;
214
215 while (x < size) {
216 te = &table[x];
217 Addr v = te->vpn << te->N;
218 if (mva >= v && mva < v + te->size) {
219 te->valid = false;
220 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
221 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
222 }
223 x++;
224 }
225}
226
227void
228TLB::serialize(ostream &os)
229{
230 panic("Implement Serialize\n");
231}
232
233void
234TLB::unserialize(Checkpoint *cp, const string §ion)
235{
236
237 panic("Need to properly unserialize TLB\n");
238}
239
240void
241TLB::regStats()
242{
243 read_hits
244 .name(name() + ".read_hits")
245 .desc("DTB read hits")
246 ;
247
248 read_misses
249 .name(name() + ".read_misses")
250 .desc("DTB read misses")
251 ;
252
253
254 read_accesses
255 .name(name() + ".read_accesses")
256 .desc("DTB read accesses")
257 ;
258
259 write_hits
260 .name(name() + ".write_hits")
261 .desc("DTB write hits")
262 ;
263
264 write_misses
265 .name(name() + ".write_misses")
266 .desc("DTB write misses")
267 ;
268
269
270 write_accesses
271 .name(name() + ".write_accesses")
272 .desc("DTB write accesses")
273 ;
274
275 hits
276 .name(name() + ".hits")
277 .desc("DTB hits")
278 ;
279
280 misses
281 .name(name() + ".misses")
282 .desc("DTB misses")
283 ;
284
285 accesses
286 .name(name() + ".accesses")
287 .desc("DTB accesses")
288 ;
289
290 hits = read_hits + write_hits;
291 misses = read_misses + write_misses;
292 accesses = read_accesses + write_accesses;
293}
294
295#if !FULL_SYSTEM
296Fault
297TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
298 Translation *translation, bool &delay, bool timing)
299{
300 // XXX Cache misc registers and have miscreg write function inv cache
301 Addr vaddr = req->getVaddr() & ~PcModeMask;
302 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
303 uint32_t flags = req->getFlags();
304
305 bool is_fetch = (mode == Execute);
306 bool is_write = (mode == Write);
307
308 if (!is_fetch) {
309 assert(flags & MustBeOne);
310 if (sctlr.a || !(flags & AllowUnaligned)) {
311 if (vaddr & flags & AlignmentMask) {
312 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
313 }
314 }
315 }
316
317 Addr paddr;
318 Process *p = tc->getProcessPtr();
319
320 if (!p->pTable->translate(vaddr, paddr))
321 return Fault(new GenericPageTableFault(vaddr));
322 req->setPaddr(paddr);
323
324 return NoFault;
325}
326
327#else // FULL_SYSTEM
328
329Fault
330TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
331{
332 return NoFault;
333}
334
335Fault
336TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
337 bool is_write, uint8_t domain, bool sNp)
338{
339 return NoFault;
340}
341
342Fault
343TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
344 Translation *translation, bool &delay, bool timing)
345{
346 // XXX Cache misc registers and have miscreg write function inv cache
347 Addr vaddr = req->getVaddr() & ~PcModeMask;
348 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
350 uint32_t flags = req->getFlags();
351
352 bool is_fetch = (mode == Execute);
353 bool is_write = (mode == Write);
354 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
355
356 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
357 & UserMode);
358 // If this is a clrex instruction, provide a PA of 0 with no fault
359 // This will force the monitor to set the tracked address to 0
360 // a bit of a hack but this effectively clrears this processors monitor
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "mem/page_table.hh"
57#include "params/ArmTLB.hh"
58#include "sim/process.hh"
59
60#if FULL_SYSTEM
61#include "arch/arm/table_walker.hh"
62#endif
63
64using namespace std;
65using namespace ArmISA;
66
67TLB::TLB(const Params *p)
68 : BaseTLB(p), size(p->size), nlu(0)
69#if FULL_SYSTEM
70 , tableWalker(p->walker)
71#endif
72{
73 table = new TlbEntry[size];
74 memset(table, 0, sizeof(TlbEntry[size]));
75
76#if FULL_SYSTEM
77 tableWalker->setTlb(this);
78#endif
79}
80
81TLB::~TLB()
82{
83 if (table)
84 delete [] table;
85}
86
87TlbEntry*
88TLB::lookup(Addr va, uint8_t cid)
89{
90 // XXX This should either turn into a TlbMap or add caching
91
92 TlbEntry *retval = NULL;
93
94 // Do some kind of caching, fast indexing, anything
95
96 int x = 0;
97 while (retval == NULL && x < size) {
98 if (table[x].match(va, cid)) {
99 retval = &table[x];
100 if (x == nlu)
101 nextnlu();
102
103 break;
104 }
105 x++;
106 }
107
108 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
109 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
110 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
111 retval ? retval->ap : 0);
112 ;
113 return retval;
114}
115
116// insert a new TLB entry
117void
118TLB::insert(Addr addr, TlbEntry &entry)
119{
120 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
121 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
122 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
123 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
124 entry.xn, entry.ap, entry.domain);
125
126 if (table[nlu].valid)
127 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
128 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N,
129 table[nlu].size, table[nlu].ap);
130
131 // XXX Update caching, lookup table etc
132 table[nlu] = entry;
133
134 // XXX Figure out how entries are generally inserted in ARM
135 nextnlu();
136}
137
138void
139TLB::printTlb()
140{
141 int x = 0;
142 TlbEntry *te;
143 DPRINTF(TLB, "Current TLB contents:\n");
144 while (x < size) {
145 te = &table[x];
146 if (te->valid)
147 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
148 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
149 x++;
150 }
151}
152
153
154void
155TLB::flushAll()
156{
157 DPRINTF(TLB, "Flushing all TLB entries\n");
158 int x = 0;
159 TlbEntry *te;
160 while (x < size) {
161 te = &table[x];
162 if (te->valid)
163 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
164 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
165 x++;
166 }
167
168 memset(table, 0, sizeof(TlbEntry[size]));
169 nlu = 0;
170}
171
172
173void
174TLB::flushMvaAsid(Addr mva, uint64_t asn)
175{
176 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
177 TlbEntry *te;
178
179 te = lookup(mva, asn);
180 while (te != NULL) {
181 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
182 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
183 te->valid = false;
184 te = lookup(mva,asn);
185 }
186}
187
188void
189TLB::flushAsid(uint64_t asn)
190{
191 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
192
193 int x = 0;
194 TlbEntry *te;
195
196 while (x < size) {
197 te = &table[x];
198 if (te->asid == asn) {
199 te->valid = false;
200 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
201 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
202 }
203 x++;
204 }
205}
206
207void
208TLB::flushMva(Addr mva)
209{
210 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
211
212 int x = 0;
213 TlbEntry *te;
214
215 while (x < size) {
216 te = &table[x];
217 Addr v = te->vpn << te->N;
218 if (mva >= v && mva < v + te->size) {
219 te->valid = false;
220 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
221 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
222 }
223 x++;
224 }
225}
226
227void
228TLB::serialize(ostream &os)
229{
230 panic("Implement Serialize\n");
231}
232
233void
234TLB::unserialize(Checkpoint *cp, const string §ion)
235{
236
237 panic("Need to properly unserialize TLB\n");
238}
239
240void
241TLB::regStats()
242{
243 read_hits
244 .name(name() + ".read_hits")
245 .desc("DTB read hits")
246 ;
247
248 read_misses
249 .name(name() + ".read_misses")
250 .desc("DTB read misses")
251 ;
252
253
254 read_accesses
255 .name(name() + ".read_accesses")
256 .desc("DTB read accesses")
257 ;
258
259 write_hits
260 .name(name() + ".write_hits")
261 .desc("DTB write hits")
262 ;
263
264 write_misses
265 .name(name() + ".write_misses")
266 .desc("DTB write misses")
267 ;
268
269
270 write_accesses
271 .name(name() + ".write_accesses")
272 .desc("DTB write accesses")
273 ;
274
275 hits
276 .name(name() + ".hits")
277 .desc("DTB hits")
278 ;
279
280 misses
281 .name(name() + ".misses")
282 .desc("DTB misses")
283 ;
284
285 accesses
286 .name(name() + ".accesses")
287 .desc("DTB accesses")
288 ;
289
290 hits = read_hits + write_hits;
291 misses = read_misses + write_misses;
292 accesses = read_accesses + write_accesses;
293}
294
295#if !FULL_SYSTEM
296Fault
297TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
298 Translation *translation, bool &delay, bool timing)
299{
300 // XXX Cache misc registers and have miscreg write function inv cache
301 Addr vaddr = req->getVaddr() & ~PcModeMask;
302 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
303 uint32_t flags = req->getFlags();
304
305 bool is_fetch = (mode == Execute);
306 bool is_write = (mode == Write);
307
308 if (!is_fetch) {
309 assert(flags & MustBeOne);
310 if (sctlr.a || !(flags & AllowUnaligned)) {
311 if (vaddr & flags & AlignmentMask) {
312 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
313 }
314 }
315 }
316
317 Addr paddr;
318 Process *p = tc->getProcessPtr();
319
320 if (!p->pTable->translate(vaddr, paddr))
321 return Fault(new GenericPageTableFault(vaddr));
322 req->setPaddr(paddr);
323
324 return NoFault;
325}
326
327#else // FULL_SYSTEM
328
329Fault
330TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
331{
332 return NoFault;
333}
334
335Fault
336TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
337 bool is_write, uint8_t domain, bool sNp)
338{
339 return NoFault;
340}
341
342Fault
343TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
344 Translation *translation, bool &delay, bool timing)
345{
346 // XXX Cache misc registers and have miscreg write function inv cache
347 Addr vaddr = req->getVaddr() & ~PcModeMask;
348 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
350 uint32_t flags = req->getFlags();
351
352 bool is_fetch = (mode == Execute);
353 bool is_write = (mode == Write);
354 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
355
356 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
357 & UserMode);
358 // If this is a clrex instruction, provide a PA of 0 with no fault
359 // This will force the monitor to set the tracked address to 0
360 // a bit of a hack but this effectively clrears this processors monitor
|
364 return NoFault;
365 }
366 if ((req->isInstFetch() && (!sctlr.i)) ||
367 ((!req->isInstFetch()) && (!sctlr.c))){
368 req->setFlags(Request::UNCACHEABLE);
369 }
370 if (!is_fetch) {
371 assert(flags & MustBeOne);
372 if (sctlr.a || !(flags & AllowUnaligned)) {
373 if (vaddr & flags & AlignmentMask) {
374 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
375 }
376 }
377 }
378
379 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
380 Fault fault;
381
382
383 if (!sctlr.m) {
384 req->setPaddr(vaddr);
385 if (sctlr.tre == 0) {
386 req->setFlags(Request::UNCACHEABLE);
387 } else {
388 PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
389 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
390
391 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
392 req->setFlags(Request::UNCACHEABLE);
393 }
394
395 // Set memory attributes
396 TlbEntry temp_te;
397 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
398 temp_te.shareable = true;
399 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
400 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
401 temp_te.innerAttrs, temp_te.outerAttrs);
402 setAttr(temp_te.attributes);
403
404 return trickBoxCheck(req, mode, 0, false);
405 }
406
407 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id);
408 // Translation enabled
409
410 TlbEntry *te = lookup(vaddr, context_id);
411 if (te == NULL) {
412 if (req->isPrefetch()){
413 //if the request is a prefetch don't attempt to fill the TLB
414 //or go any further with the memory access
415 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
416 }
417 // start translation table walk, pass variables rather than
418 // re-retreaving in table walker for speed
419 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
420 vaddr, context_id);
421 fault = tableWalker->walk(req, tc, context_id, mode, translation,
422 timing);
423 if (timing) {
424 delay = true;
425 // for timing mode, return and wait for table walk
426 return fault;
427 }
428 if (fault)
429 return fault;
430
431 te = lookup(vaddr, context_id);
432 if (!te)
433 printTlb();
434 assert(te);
435 }
436
437 // Set memory attributes
438 DPRINTF(TLBVerbose,
439 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
440 outerAttrs: %d\n",
441 te->shareable, te->innerAttrs, te->outerAttrs);
442 setAttr(te->attributes);
443 if (te->nonCacheable)
444 req->setFlags(Request::UNCACHEABLE);
445 uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
446 switch ( (dacr >> (te->domain * 2)) & 0x3) {
447 case 0:
448 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
449 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
450 if (is_fetch)
451 return new PrefetchAbort(vaddr,
452 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
453 else
454 return new DataAbort(vaddr, te->domain, is_write,
455 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
456 case 1:
457 // Continue with permissions check
458 break;
459 case 2:
460 panic("UNPRED domain\n");
461 case 3:
462 req->setPaddr(te->pAddr(vaddr));
463 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
464 if (fault)
465 return fault;
466 return NoFault;
467 }
468
469 uint8_t ap = te->ap;
470
471 if (sctlr.afe == 1)
472 ap |= 1;
473
474 bool abt;
475
476 /* if (!sctlr.xp)
477 ap &= 0x3;
478*/
479 switch (ap) {
480 case 0:
481 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
482 if (!sctlr.xp) {
483 switch ((int)sctlr.rs) {
484 case 2:
485 abt = is_write;
486 break;
487 case 1:
488 abt = is_write || !is_priv;
489 break;
490 case 0:
491 case 3:
492 default:
493 abt = true;
494 break;
495 }
496 } else {
497 abt = true;
498 }
499 break;
500 case 1:
501 abt = !is_priv;
502 break;
503 case 2:
504 abt = !is_priv && is_write;
505 break;
506 case 3:
507 abt = false;
508 break;
509 case 4:
510 panic("UNPRED premissions\n");
511 case 5:
512 abt = !is_priv || is_write;
513 break;
514 case 6:
515 case 7:
516 abt = is_write;
517 break;
518 default:
519 panic("Unknown permissions\n");
520 }
521 if ((is_fetch) && (abt || te->xn)) {
522 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
523 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
524 return new PrefetchAbort(vaddr,
525 (te->sNp ? ArmFault::Permission0 :
526 ArmFault::Permission1));
527 } else if (abt) {
528 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
529 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
530 return new DataAbort(vaddr, te->domain, is_write,
531 (te->sNp ? ArmFault::Permission0 :
532 ArmFault::Permission1));
533 }
534
535 req->setPaddr(te->pAddr(vaddr));
536 // Check for a trickbox generated address fault
537 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
538 if (fault)
539 return fault;
540
541 return NoFault;
542}
543
544#endif
545
546Fault
547TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
548{
549 bool delay = false;
550 Fault fault;
551#if FULL_SYSTEM
552 fault = translateFs(req, tc, mode, NULL, delay, false);
553#else
554 fault = translateSe(req, tc, mode, NULL, delay, false);
555#endif
556 assert(!delay);
557 return fault;
558}
559
560Fault
561TLB::translateTiming(RequestPtr req, ThreadContext *tc,
562 Translation *translation, Mode mode)
563{
564 assert(translation);
565 bool delay = false;
566 Fault fault;
567#if FULL_SYSTEM
568 fault = translateFs(req, tc, mode, translation, delay, true);
569#else
570 fault = translateSe(req, tc, mode, translation, delay, true);
571#endif
572 if (!delay)
573 translation->finish(fault, req, tc, mode);
574 return fault;
575}
576
577ArmISA::TLB *
578ArmTLBParams::create()
579{
580 return new ArmISA::TLB(this);
581}
| 365 return NoFault;
366 }
367 if ((req->isInstFetch() && (!sctlr.i)) ||
368 ((!req->isInstFetch()) && (!sctlr.c))){
369 req->setFlags(Request::UNCACHEABLE);
370 }
371 if (!is_fetch) {
372 assert(flags & MustBeOne);
373 if (sctlr.a || !(flags & AllowUnaligned)) {
374 if (vaddr & flags & AlignmentMask) {
375 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
376 }
377 }
378 }
379
380 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
381 Fault fault;
382
383
384 if (!sctlr.m) {
385 req->setPaddr(vaddr);
386 if (sctlr.tre == 0) {
387 req->setFlags(Request::UNCACHEABLE);
388 } else {
389 PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
390 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
391
392 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
393 req->setFlags(Request::UNCACHEABLE);
394 }
395
396 // Set memory attributes
397 TlbEntry temp_te;
398 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
399 temp_te.shareable = true;
400 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
401 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
402 temp_te.innerAttrs, temp_te.outerAttrs);
403 setAttr(temp_te.attributes);
404
405 return trickBoxCheck(req, mode, 0, false);
406 }
407
408 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id);
409 // Translation enabled
410
411 TlbEntry *te = lookup(vaddr, context_id);
412 if (te == NULL) {
413 if (req->isPrefetch()){
414 //if the request is a prefetch don't attempt to fill the TLB
415 //or go any further with the memory access
416 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
417 }
418 // start translation table walk, pass variables rather than
419 // re-retreaving in table walker for speed
420 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
421 vaddr, context_id);
422 fault = tableWalker->walk(req, tc, context_id, mode, translation,
423 timing);
424 if (timing) {
425 delay = true;
426 // for timing mode, return and wait for table walk
427 return fault;
428 }
429 if (fault)
430 return fault;
431
432 te = lookup(vaddr, context_id);
433 if (!te)
434 printTlb();
435 assert(te);
436 }
437
438 // Set memory attributes
439 DPRINTF(TLBVerbose,
440 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
441 outerAttrs: %d\n",
442 te->shareable, te->innerAttrs, te->outerAttrs);
443 setAttr(te->attributes);
444 if (te->nonCacheable)
445 req->setFlags(Request::UNCACHEABLE);
446 uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
447 switch ( (dacr >> (te->domain * 2)) & 0x3) {
448 case 0:
449 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
450 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
451 if (is_fetch)
452 return new PrefetchAbort(vaddr,
453 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
454 else
455 return new DataAbort(vaddr, te->domain, is_write,
456 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
457 case 1:
458 // Continue with permissions check
459 break;
460 case 2:
461 panic("UNPRED domain\n");
462 case 3:
463 req->setPaddr(te->pAddr(vaddr));
464 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
465 if (fault)
466 return fault;
467 return NoFault;
468 }
469
470 uint8_t ap = te->ap;
471
472 if (sctlr.afe == 1)
473 ap |= 1;
474
475 bool abt;
476
477 /* if (!sctlr.xp)
478 ap &= 0x3;
479*/
480 switch (ap) {
481 case 0:
482 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
483 if (!sctlr.xp) {
484 switch ((int)sctlr.rs) {
485 case 2:
486 abt = is_write;
487 break;
488 case 1:
489 abt = is_write || !is_priv;
490 break;
491 case 0:
492 case 3:
493 default:
494 abt = true;
495 break;
496 }
497 } else {
498 abt = true;
499 }
500 break;
501 case 1:
502 abt = !is_priv;
503 break;
504 case 2:
505 abt = !is_priv && is_write;
506 break;
507 case 3:
508 abt = false;
509 break;
510 case 4:
511 panic("UNPRED premissions\n");
512 case 5:
513 abt = !is_priv || is_write;
514 break;
515 case 6:
516 case 7:
517 abt = is_write;
518 break;
519 default:
520 panic("Unknown permissions\n");
521 }
522 if ((is_fetch) && (abt || te->xn)) {
523 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
524 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
525 return new PrefetchAbort(vaddr,
526 (te->sNp ? ArmFault::Permission0 :
527 ArmFault::Permission1));
528 } else if (abt) {
529 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
530 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
531 return new DataAbort(vaddr, te->domain, is_write,
532 (te->sNp ? ArmFault::Permission0 :
533 ArmFault::Permission1));
534 }
535
536 req->setPaddr(te->pAddr(vaddr));
537 // Check for a trickbox generated address fault
538 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
539 if (fault)
540 return fault;
541
542 return NoFault;
543}
544
545#endif
546
547Fault
548TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
549{
550 bool delay = false;
551 Fault fault;
552#if FULL_SYSTEM
553 fault = translateFs(req, tc, mode, NULL, delay, false);
554#else
555 fault = translateSe(req, tc, mode, NULL, delay, false);
556#endif
557 assert(!delay);
558 return fault;
559}
560
561Fault
562TLB::translateTiming(RequestPtr req, ThreadContext *tc,
563 Translation *translation, Mode mode)
564{
565 assert(translation);
566 bool delay = false;
567 Fault fault;
568#if FULL_SYSTEM
569 fault = translateFs(req, tc, mode, translation, delay, true);
570#else
571 fault = translateSe(req, tc, mode, translation, delay, true);
572#endif
573 if (!delay)
574 translation->finish(fault, req, tc, mode);
575 return fault;
576}
577
578ArmISA::TLB *
579ArmTLBParams::create()
580{
581 return new ArmISA::TLB(this);
582}
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