1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "mem/page_table.hh"
57#include "params/ArmTLB.hh"
58#include "sim/process.hh"
59
60#if FULL_SYSTEM
61#include "arch/arm/table_walker.hh"
62#endif
63
64using namespace std;
65using namespace ArmISA;
66
67TLB::TLB(const Params *p)
68 : BaseTLB(p), size(p->size), nlu(0)
69#if FULL_SYSTEM
70 , tableWalker(p->walker)
71#endif
72{
73 table = new TlbEntry[size];
74 memset(table, 0, sizeof(TlbEntry[size]));
75
76#if FULL_SYSTEM
77 tableWalker->setTlb(this);
78#endif
79}
80
81TLB::~TLB()
82{
83 if (table)
84 delete [] table;
85}
86
87TlbEntry*
88TLB::lookup(Addr va, uint8_t cid)
89{
90 // XXX This should either turn into a TlbMap or add caching
91
92 TlbEntry *retval = NULL;
93
94 // Do some kind of caching, fast indexing, anything
95
96 int x = 0;
97 while (retval == NULL && x < size) {
98 if (table[x].match(va, cid)) {
99 retval = &table[x];
100 if (x == nlu)
101 nextnlu();
102
103 break;
104 }
105 x++;
106 }
107
108 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
109 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
110 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
111 retval ? retval->ap : 0);
112 ;
113 return retval;
114}
115
116// insert a new TLB entry
117void
118TLB::insert(Addr addr, TlbEntry &entry)
119{
120 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
121 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
122 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
123 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
124 entry.xn, entry.ap, entry.domain);
125
126 if (table[nlu].valid)
127 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
128 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N,
129 table[nlu].size, table[nlu].ap);
130
131 // XXX Update caching, lookup table etc
132 table[nlu] = entry;
133
134 // XXX Figure out how entries are generally inserted in ARM
135 nextnlu();
136}
137
138void
139TLB::printTlb()
140{
141 int x = 0;
142 TlbEntry *te;
143 DPRINTF(TLB, "Current TLB contents:\n");
144 while (x < size) {
145 te = &table[x];
146 if (te->valid)
147 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
148 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
149 x++;
150 }
151}
152
153
154void
155TLB::flushAll()
156{
157 DPRINTF(TLB, "Flushing all TLB entries\n");
158 int x = 0;
159 TlbEntry *te;
160 while (x < size) {
161 te = &table[x];
162 if (te->valid)
163 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
164 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
165 x++;
166 }
167
168 memset(table, 0, sizeof(TlbEntry[size]));
169 nlu = 0;
170}
171
172
173void
174TLB::flushMvaAsid(Addr mva, uint64_t asn)
175{
176 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
177 TlbEntry *te;
178
179 te = lookup(mva, asn);
180 while (te != NULL) {
181 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
182 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
183 te->valid = false;
184 te = lookup(mva,asn);
185 }
186}
187
188void
189TLB::flushAsid(uint64_t asn)
190{
191 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
192
193 int x = 0;
194 TlbEntry *te;
195
196 while (x < size) {
197 te = &table[x];
198 if (te->asid == asn) {
199 te->valid = false;
200 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
201 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
202 }
203 x++;
204 }
205}
206
207void
208TLB::flushMva(Addr mva)
209{
210 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
211
212 int x = 0;
213 TlbEntry *te;
214
215 while (x < size) {
216 te = &table[x];
217 Addr v = te->vpn << te->N;
218 if (mva >= v && mva < v + te->size) {
219 te->valid = false;
220 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
221 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
222 }
223 x++;
224 }
225}
226
227void
228TLB::serialize(ostream &os)
229{
230 panic("Implement Serialize\n");
231}
232
233void
234TLB::unserialize(Checkpoint *cp, const string §ion)
235{
236
237 panic("Need to properly unserialize TLB\n");
238}
239
240void
241TLB::regStats()
242{
243 read_hits
244 .name(name() + ".read_hits")
245 .desc("DTB read hits")
246 ;
247
248 read_misses
249 .name(name() + ".read_misses")
250 .desc("DTB read misses")
251 ;
252
253
254 read_accesses
255 .name(name() + ".read_accesses")
256 .desc("DTB read accesses")
257 ;
258
259 write_hits
260 .name(name() + ".write_hits")
261 .desc("DTB write hits")
262 ;
263
264 write_misses
265 .name(name() + ".write_misses")
266 .desc("DTB write misses")
267 ;
268
269
270 write_accesses
271 .name(name() + ".write_accesses")
272 .desc("DTB write accesses")
273 ;
274
275 hits
276 .name(name() + ".hits")
277 .desc("DTB hits")
278 ;
279
280 misses
281 .name(name() + ".misses")
282 .desc("DTB misses")
283 ;
284
285 accesses
286 .name(name() + ".accesses")
287 .desc("DTB accesses")
288 ;
289
290 hits = read_hits + write_hits;
291 misses = read_misses + write_misses;
292 accesses = read_accesses + write_accesses;
293}
294
295#if !FULL_SYSTEM
296Fault
297TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
298 Translation *translation, bool &delay, bool timing)
299{
300 // XXX Cache misc registers and have miscreg write function inv cache
301 Addr vaddr = req->getVaddr() & ~PcModeMask;
302 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
303 uint32_t flags = req->getFlags();
304
305 bool is_fetch = (mode == Execute);
306 bool is_write = (mode == Write);
307
308 if (!is_fetch) {
309 assert(flags & MustBeOne);
310 if (sctlr.a || !(flags & AllowUnaligned)) {
311 if (vaddr & flags & AlignmentMask) {
312 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
313 }
314 }
315 }
316
317 Addr paddr;
318 Process *p = tc->getProcessPtr();
319
320 if (!p->pTable->translate(vaddr, paddr))
321 return Fault(new GenericPageTableFault(vaddr));
322 req->setPaddr(paddr);
323
324 return NoFault;
325}
326
327#else // FULL_SYSTEM
328
329Fault
330TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
331{
332 return NoFault;
333}
334
335Fault
336TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
337 bool is_write, uint8_t domain, bool sNp)
338{
339 return NoFault;
340}
341
342Fault
343TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
344 Translation *translation, bool &delay, bool timing)
345{
346 // XXX Cache misc registers and have miscreg write function inv cache
347 Addr vaddr = req->getVaddr() & ~PcModeMask;
348 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
350 uint32_t flags = req->getFlags();
351
352 bool is_fetch = (mode == Execute);
353 bool is_write = (mode == Write);
354 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
355
356 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
357 & UserMode);
358 // If this is a clrex instruction, provide a PA of 0 with no fault
359 // This will force the monitor to set the tracked address to 0
360 // a bit of a hack but this effectively clrears this processors monitor
361 if (flags & Clrex){
362 req->setPaddr(0);
363 req->setFlags(Request::UNCACHEABLE);
364 return NoFault;
365 }
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "mem/page_table.hh"
57#include "params/ArmTLB.hh"
58#include "sim/process.hh"
59
60#if FULL_SYSTEM
61#include "arch/arm/table_walker.hh"
62#endif
63
64using namespace std;
65using namespace ArmISA;
66
67TLB::TLB(const Params *p)
68 : BaseTLB(p), size(p->size), nlu(0)
69#if FULL_SYSTEM
70 , tableWalker(p->walker)
71#endif
72{
73 table = new TlbEntry[size];
74 memset(table, 0, sizeof(TlbEntry[size]));
75
76#if FULL_SYSTEM
77 tableWalker->setTlb(this);
78#endif
79}
80
81TLB::~TLB()
82{
83 if (table)
84 delete [] table;
85}
86
87TlbEntry*
88TLB::lookup(Addr va, uint8_t cid)
89{
90 // XXX This should either turn into a TlbMap or add caching
91
92 TlbEntry *retval = NULL;
93
94 // Do some kind of caching, fast indexing, anything
95
96 int x = 0;
97 while (retval == NULL && x < size) {
98 if (table[x].match(va, cid)) {
99 retval = &table[x];
100 if (x == nlu)
101 nextnlu();
102
103 break;
104 }
105 x++;
106 }
107
108 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
109 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
110 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
111 retval ? retval->ap : 0);
112 ;
113 return retval;
114}
115
116// insert a new TLB entry
117void
118TLB::insert(Addr addr, TlbEntry &entry)
119{
120 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
121 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
122 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
123 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
124 entry.xn, entry.ap, entry.domain);
125
126 if (table[nlu].valid)
127 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
128 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N,
129 table[nlu].size, table[nlu].ap);
130
131 // XXX Update caching, lookup table etc
132 table[nlu] = entry;
133
134 // XXX Figure out how entries are generally inserted in ARM
135 nextnlu();
136}
137
138void
139TLB::printTlb()
140{
141 int x = 0;
142 TlbEntry *te;
143 DPRINTF(TLB, "Current TLB contents:\n");
144 while (x < size) {
145 te = &table[x];
146 if (te->valid)
147 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
148 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
149 x++;
150 }
151}
152
153
154void
155TLB::flushAll()
156{
157 DPRINTF(TLB, "Flushing all TLB entries\n");
158 int x = 0;
159 TlbEntry *te;
160 while (x < size) {
161 te = &table[x];
162 if (te->valid)
163 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
164 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
165 x++;
166 }
167
168 memset(table, 0, sizeof(TlbEntry[size]));
169 nlu = 0;
170}
171
172
173void
174TLB::flushMvaAsid(Addr mva, uint64_t asn)
175{
176 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
177 TlbEntry *te;
178
179 te = lookup(mva, asn);
180 while (te != NULL) {
181 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
182 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
183 te->valid = false;
184 te = lookup(mva,asn);
185 }
186}
187
188void
189TLB::flushAsid(uint64_t asn)
190{
191 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
192
193 int x = 0;
194 TlbEntry *te;
195
196 while (x < size) {
197 te = &table[x];
198 if (te->asid == asn) {
199 te->valid = false;
200 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
201 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
202 }
203 x++;
204 }
205}
206
207void
208TLB::flushMva(Addr mva)
209{
210 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
211
212 int x = 0;
213 TlbEntry *te;
214
215 while (x < size) {
216 te = &table[x];
217 Addr v = te->vpn << te->N;
218 if (mva >= v && mva < v + te->size) {
219 te->valid = false;
220 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
221 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
222 }
223 x++;
224 }
225}
226
227void
228TLB::serialize(ostream &os)
229{
230 panic("Implement Serialize\n");
231}
232
233void
234TLB::unserialize(Checkpoint *cp, const string §ion)
235{
236
237 panic("Need to properly unserialize TLB\n");
238}
239
240void
241TLB::regStats()
242{
243 read_hits
244 .name(name() + ".read_hits")
245 .desc("DTB read hits")
246 ;
247
248 read_misses
249 .name(name() + ".read_misses")
250 .desc("DTB read misses")
251 ;
252
253
254 read_accesses
255 .name(name() + ".read_accesses")
256 .desc("DTB read accesses")
257 ;
258
259 write_hits
260 .name(name() + ".write_hits")
261 .desc("DTB write hits")
262 ;
263
264 write_misses
265 .name(name() + ".write_misses")
266 .desc("DTB write misses")
267 ;
268
269
270 write_accesses
271 .name(name() + ".write_accesses")
272 .desc("DTB write accesses")
273 ;
274
275 hits
276 .name(name() + ".hits")
277 .desc("DTB hits")
278 ;
279
280 misses
281 .name(name() + ".misses")
282 .desc("DTB misses")
283 ;
284
285 accesses
286 .name(name() + ".accesses")
287 .desc("DTB accesses")
288 ;
289
290 hits = read_hits + write_hits;
291 misses = read_misses + write_misses;
292 accesses = read_accesses + write_accesses;
293}
294
295#if !FULL_SYSTEM
296Fault
297TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
298 Translation *translation, bool &delay, bool timing)
299{
300 // XXX Cache misc registers and have miscreg write function inv cache
301 Addr vaddr = req->getVaddr() & ~PcModeMask;
302 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
303 uint32_t flags = req->getFlags();
304
305 bool is_fetch = (mode == Execute);
306 bool is_write = (mode == Write);
307
308 if (!is_fetch) {
309 assert(flags & MustBeOne);
310 if (sctlr.a || !(flags & AllowUnaligned)) {
311 if (vaddr & flags & AlignmentMask) {
312 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
313 }
314 }
315 }
316
317 Addr paddr;
318 Process *p = tc->getProcessPtr();
319
320 if (!p->pTable->translate(vaddr, paddr))
321 return Fault(new GenericPageTableFault(vaddr));
322 req->setPaddr(paddr);
323
324 return NoFault;
325}
326
327#else // FULL_SYSTEM
328
329Fault
330TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
331{
332 return NoFault;
333}
334
335Fault
336TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
337 bool is_write, uint8_t domain, bool sNp)
338{
339 return NoFault;
340}
341
342Fault
343TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
344 Translation *translation, bool &delay, bool timing)
345{
346 // XXX Cache misc registers and have miscreg write function inv cache
347 Addr vaddr = req->getVaddr() & ~PcModeMask;
348 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
350 uint32_t flags = req->getFlags();
351
352 bool is_fetch = (mode == Execute);
353 bool is_write = (mode == Write);
354 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
355
356 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
357 & UserMode);
358 // If this is a clrex instruction, provide a PA of 0 with no fault
359 // This will force the monitor to set the tracked address to 0
360 // a bit of a hack but this effectively clrears this processors monitor
361 if (flags & Clrex){
362 req->setPaddr(0);
363 req->setFlags(Request::UNCACHEABLE);
364 return NoFault;
365 }
|
366 if (!is_fetch) {
367 assert(flags & MustBeOne);
368 if (sctlr.a || !(flags & AllowUnaligned)) {
369 if (vaddr & flags & AlignmentMask) {
370 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
371 }
372 }
373 }
374
375 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
376 Fault fault;
377
378
379 if (!sctlr.m) {
380 req->setPaddr(vaddr);
381 if (sctlr.tre == 0) {
382 req->setFlags(Request::UNCACHEABLE);
383 } else {
384 PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
385 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
386
387 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
388 req->setFlags(Request::UNCACHEABLE);
389 }
390
391 // Set memory attributes
392 TlbEntry temp_te;
393 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
394 temp_te.shareable = true;
395 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
396 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
397 temp_te.innerAttrs, temp_te.outerAttrs);
398 setAttr(temp_te.attributes);
399
400 return trickBoxCheck(req, mode, 0, false);
401 }
402
403 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id);
404 // Translation enabled
405
406 TlbEntry *te = lookup(vaddr, context_id);
407 if (te == NULL) {
408 // start translation table walk, pass variables rather than
409 // re-retreaving in table walker for speed
410 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
411 vaddr, context_id);
412 fault = tableWalker->walk(req, tc, context_id, mode, translation,
413 timing);
414 if (timing) {
415 delay = true;
416 // for timing mode, return and wait for table walk
417 return fault;
418 }
419 if (fault)
420 return fault;
421
422 te = lookup(vaddr, context_id);
423 if (!te)
424 printTlb();
425 assert(te);
426 }
427
428 // Set memory attributes
429 DPRINTF(TLBVerbose,
430 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
431 outerAttrs: %d\n",
432 te->shareable, te->innerAttrs, te->outerAttrs);
433 setAttr(te->attributes);
434 if (te->nonCacheable)
435 req->setFlags(Request::UNCACHEABLE);
436 uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
437 switch ( (dacr >> (te->domain * 2)) & 0x3) {
438 case 0:
439 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
440 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
441 if (is_fetch)
442 return new PrefetchAbort(vaddr,
443 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
444 else
445 return new DataAbort(vaddr, te->domain, is_write,
446 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
447 case 1:
448 // Continue with permissions check
449 break;
450 case 2:
451 panic("UNPRED domain\n");
452 case 3:
453 req->setPaddr(te->pAddr(vaddr));
454 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
455 if (fault)
456 return fault;
457 return NoFault;
458 }
459
460 uint8_t ap = te->ap;
461
462 if (sctlr.afe == 1)
463 ap |= 1;
464
465 bool abt;
466
467 /* if (!sctlr.xp)
468 ap &= 0x3;
469*/
470 switch (ap) {
471 case 0:
472 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
473 if (!sctlr.xp) {
474 switch ((int)sctlr.rs) {
475 case 2:
476 abt = is_write;
477 break;
478 case 1:
479 abt = is_write || !is_priv;
480 break;
481 case 0:
482 case 3:
483 default:
484 abt = true;
485 break;
486 }
487 } else {
488 abt = true;
489 }
490 break;
491 case 1:
492 abt = !is_priv;
493 break;
494 case 2:
495 abt = !is_priv && is_write;
496 break;
497 case 3:
498 abt = false;
499 break;
500 case 4:
501 panic("UNPRED premissions\n");
502 case 5:
503 abt = !is_priv || is_write;
504 break;
505 case 6:
506 case 7:
507 abt = is_write;
508 break;
509 default:
510 panic("Unknown permissions\n");
511 }
512 if ((is_fetch) && (abt || te->xn)) {
513 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
514 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
515 return new PrefetchAbort(vaddr,
516 (te->sNp ? ArmFault::Permission0 :
517 ArmFault::Permission1));
518 } else if (abt) {
519 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
520 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
521 return new DataAbort(vaddr, te->domain, is_write,
522 (te->sNp ? ArmFault::Permission0 :
523 ArmFault::Permission1));
524 }
525
526 req->setPaddr(te->pAddr(vaddr));
527 // Check for a trickbox generated address fault
528 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
529 if (fault)
530 return fault;
531
532 return NoFault;
533}
534
535#endif
536
537Fault
538TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
539{
540 bool delay = false;
541 Fault fault;
542#if FULL_SYSTEM
543 fault = translateFs(req, tc, mode, NULL, delay, false);
544#else
545 fault = translateSe(req, tc, mode, NULL, delay, false);
546#endif
547 assert(!delay);
548 return fault;
549}
550
551Fault
552TLB::translateTiming(RequestPtr req, ThreadContext *tc,
553 Translation *translation, Mode mode)
554{
555 assert(translation);
556 bool delay = false;
557 Fault fault;
558#if FULL_SYSTEM
559 fault = translateFs(req, tc, mode, translation, delay, true);
560#else
561 fault = translateSe(req, tc, mode, translation, delay, true);
562#endif
563 if (!delay)
564 translation->finish(fault, req, tc, mode);
565 return fault;
566}
567
568ArmISA::TLB *
569ArmTLBParams::create()
570{
571 return new ArmISA::TLB(this);
572}
| 370 if (!is_fetch) {
371 assert(flags & MustBeOne);
372 if (sctlr.a || !(flags & AllowUnaligned)) {
373 if (vaddr & flags & AlignmentMask) {
374 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
375 }
376 }
377 }
378
379 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
380 Fault fault;
381
382
383 if (!sctlr.m) {
384 req->setPaddr(vaddr);
385 if (sctlr.tre == 0) {
386 req->setFlags(Request::UNCACHEABLE);
387 } else {
388 PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
389 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
390
391 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
392 req->setFlags(Request::UNCACHEABLE);
393 }
394
395 // Set memory attributes
396 TlbEntry temp_te;
397 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
398 temp_te.shareable = true;
399 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
400 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
401 temp_te.innerAttrs, temp_te.outerAttrs);
402 setAttr(temp_te.attributes);
403
404 return trickBoxCheck(req, mode, 0, false);
405 }
406
407 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id);
408 // Translation enabled
409
410 TlbEntry *te = lookup(vaddr, context_id);
411 if (te == NULL) {
412 // start translation table walk, pass variables rather than
413 // re-retreaving in table walker for speed
414 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
415 vaddr, context_id);
416 fault = tableWalker->walk(req, tc, context_id, mode, translation,
417 timing);
418 if (timing) {
419 delay = true;
420 // for timing mode, return and wait for table walk
421 return fault;
422 }
423 if (fault)
424 return fault;
425
426 te = lookup(vaddr, context_id);
427 if (!te)
428 printTlb();
429 assert(te);
430 }
431
432 // Set memory attributes
433 DPRINTF(TLBVerbose,
434 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
435 outerAttrs: %d\n",
436 te->shareable, te->innerAttrs, te->outerAttrs);
437 setAttr(te->attributes);
438 if (te->nonCacheable)
439 req->setFlags(Request::UNCACHEABLE);
440 uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
441 switch ( (dacr >> (te->domain * 2)) & 0x3) {
442 case 0:
443 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
444 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
445 if (is_fetch)
446 return new PrefetchAbort(vaddr,
447 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
448 else
449 return new DataAbort(vaddr, te->domain, is_write,
450 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
451 case 1:
452 // Continue with permissions check
453 break;
454 case 2:
455 panic("UNPRED domain\n");
456 case 3:
457 req->setPaddr(te->pAddr(vaddr));
458 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
459 if (fault)
460 return fault;
461 return NoFault;
462 }
463
464 uint8_t ap = te->ap;
465
466 if (sctlr.afe == 1)
467 ap |= 1;
468
469 bool abt;
470
471 /* if (!sctlr.xp)
472 ap &= 0x3;
473*/
474 switch (ap) {
475 case 0:
476 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
477 if (!sctlr.xp) {
478 switch ((int)sctlr.rs) {
479 case 2:
480 abt = is_write;
481 break;
482 case 1:
483 abt = is_write || !is_priv;
484 break;
485 case 0:
486 case 3:
487 default:
488 abt = true;
489 break;
490 }
491 } else {
492 abt = true;
493 }
494 break;
495 case 1:
496 abt = !is_priv;
497 break;
498 case 2:
499 abt = !is_priv && is_write;
500 break;
501 case 3:
502 abt = false;
503 break;
504 case 4:
505 panic("UNPRED premissions\n");
506 case 5:
507 abt = !is_priv || is_write;
508 break;
509 case 6:
510 case 7:
511 abt = is_write;
512 break;
513 default:
514 panic("Unknown permissions\n");
515 }
516 if ((is_fetch) && (abt || te->xn)) {
517 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
518 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
519 return new PrefetchAbort(vaddr,
520 (te->sNp ? ArmFault::Permission0 :
521 ArmFault::Permission1));
522 } else if (abt) {
523 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
524 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
525 return new DataAbort(vaddr, te->domain, is_write,
526 (te->sNp ? ArmFault::Permission0 :
527 ArmFault::Permission1));
528 }
529
530 req->setPaddr(te->pAddr(vaddr));
531 // Check for a trickbox generated address fault
532 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
533 if (fault)
534 return fault;
535
536 return NoFault;
537}
538
539#endif
540
541Fault
542TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
543{
544 bool delay = false;
545 Fault fault;
546#if FULL_SYSTEM
547 fault = translateFs(req, tc, mode, NULL, delay, false);
548#else
549 fault = translateSe(req, tc, mode, NULL, delay, false);
550#endif
551 assert(!delay);
552 return fault;
553}
554
555Fault
556TLB::translateTiming(RequestPtr req, ThreadContext *tc,
557 Translation *translation, Mode mode)
558{
559 assert(translation);
560 bool delay = false;
561 Fault fault;
562#if FULL_SYSTEM
563 fault = translateFs(req, tc, mode, translation, delay, true);
564#else
565 fault = translateSe(req, tc, mode, translation, delay, true);
566#endif
567 if (!delay)
568 translation->finish(fault, req, tc, mode);
569 return fault;
570}
571
572ArmISA::TLB *
573ArmTLBParams::create()
574{
575 return new ArmISA::TLB(this);
576}
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