1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh"
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh"
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| 50#include "arch/arm/table_walker.hh"
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50#include "arch/arm/tlb.hh" 51#include "arch/arm/utility.hh" 52#include "base/inifile.hh" 53#include "base/str.hh" 54#include "base/trace.hh" 55#include "cpu/thread_context.hh" 56#include "mem/page_table.hh" 57#include "params/ArmTLB.hh" 58#include "sim/process.hh" 59
| 51#include "arch/arm/tlb.hh" 52#include "arch/arm/utility.hh" 53#include "base/inifile.hh" 54#include "base/str.hh" 55#include "base/trace.hh" 56#include "cpu/thread_context.hh" 57#include "mem/page_table.hh" 58#include "params/ArmTLB.hh" 59#include "sim/process.hh" 60
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60
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61using namespace std; 62using namespace ArmISA; 63 64TLB::TLB(const Params *p) 65 : BaseTLB(p), size(p->size), nlu(0)
| 61using namespace std; 62using namespace ArmISA; 63 64TLB::TLB(const Params *p) 65 : BaseTLB(p), size(p->size), nlu(0)
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| 66#if FULL_SYSTEM 67 , tableWalker(p->walker) 68#endif
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66{
| 69{
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67 table = new ArmISA::PTE[size]; 68 memset(table, 0, sizeof(ArmISA::PTE[size]));
| 70 table = new TlbEntry[size]; 71 memset(table, 0, sizeof(TlbEntry[size]));
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69
| 72
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| 73 tableWalker->setTlb(this);
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70} 71 72TLB::~TLB() 73{ 74 if (table) 75 delete [] table; 76} 77
| 74} 75 76TLB::~TLB() 77{ 78 if (table) 79 delete [] table; 80} 81
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78ArmISA::PTE * 79TLB::lookup(Addr vpn, uint8_t asn) const
| 82TlbEntry* 83TLB::lookup(Addr va, uint8_t cid)
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80{
| 84{
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81 panic("lookup() not implemented for ARM\n");
| 85 // XXX This should either turn into a TlbMap or add caching 86 87 TlbEntry *retval = NULL; 88 89 // Do some kind of caching, fast indexing, anything 90 91 int x = 0; 92 while (retval == NULL && x < size) { 93 if (table[x].match(va, cid)) { 94 retval = &table[x]; 95 if (x == nlu) 96 nextnlu(); 97 98 break; 99 } 100 x++; 101 } 102 103 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 104 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 105 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 106 retval ? retval->ap : 0); 107 ; 108 return retval;
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82} 83 84// insert a new TLB entry 85void
| 109} 110 111// insert a new TLB entry 112void
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86TLB::insert(Addr addr, ArmISA::PTE &pte)
| 113TLB::insert(Addr addr, TlbEntry &entry)
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87{
| 114{
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88 fatal("TLB Insert not yet implemented\n");
| 115 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 116 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 117 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 118 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 119 entry.xn, entry.ap, entry.domain); 120 121 if (table[nlu].valid) 122 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 123 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N, 124 table[nlu].size, table[nlu].ap); 125 126 // XXX Update caching, lookup table etc 127 table[nlu] = entry; 128 129 // XXX Figure out how entries are generally inserted in ARM 130 nextnlu();
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89} 90 91void
| 131} 132 133void
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| 134TLB::printTlb() 135{ 136 int x = 0; 137 TlbEntry *te; 138 DPRINTF(TLB, "Current TLB contents:\n"); 139 while (x < size) { 140 te = &table[x]; 141 if (te->valid) 142 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 143 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 144 x++; 145 } 146} 147 148 149void
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92TLB::flushAll() 93{
| 150TLB::flushAll() 151{
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94 DPRINTF(TLB, "flushAll\n"); 95 memset(table, 0, sizeof(ArmISA::PTE[size])); 96 lookupTable.clear();
| 152 DPRINTF(TLB, "Flushing all TLB entries\n"); 153 int x = 0; 154 TlbEntry *te; 155 while (x < size) { 156 te = &table[x]; 157 if (te->valid) 158 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 159 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 160 x++; 161 } 162 163 memset(table, 0, sizeof(TlbEntry[size]));
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97 nlu = 0; 98} 99
| 164 nlu = 0; 165} 166
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| 167
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100void
| 168void
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101TLB::serialize(ostream &os)
| 169TLB::flushMvaAsid(Addr mva, uint64_t asn)
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102{
| 170{
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103 SERIALIZE_SCALAR(size); 104 SERIALIZE_SCALAR(nlu);
| 171 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 172 TlbEntry *te;
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105
| 173
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106 for (int i = 0; i < size; i++) { 107 nameOut(os, csprintf("%s.PTE%d", name(), i)); 108 table[i].serialize(os);
| 174 te = lookup(mva, asn); 175 while (te != NULL) { 176 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 177 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 178 te->valid = false; 179 te = lookup(mva,asn);
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109 } 110} 111 112void
| 180 } 181} 182 183void
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| 184TLB::flushAsid(uint64_t asn) 185{ 186 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 187 188 int x = 0; 189 TlbEntry *te; 190 191 while (x < size) { 192 te = &table[x]; 193 if (te->asid == asn) { 194 te->valid = false; 195 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 196 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 197 } 198 x++; 199 } 200} 201 202void 203TLB::flushMva(Addr mva) 204{ 205 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 206 207 int x = 0; 208 TlbEntry *te; 209 210 while (x < size) { 211 te = &table[x]; 212 Addr v = te->vpn << te->N; 213 if (mva >= v && mva < v + te->size) { 214 te->valid = false; 215 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 216 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 217 } 218 x++; 219 } 220} 221 222void 223TLB::serialize(ostream &os) 224{ 225 panic("Implement Serialize\n"); 226} 227 228void
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113TLB::unserialize(Checkpoint *cp, const string §ion) 114{
| 229TLB::unserialize(Checkpoint *cp, const string §ion) 230{
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115 UNSERIALIZE_SCALAR(size); 116 UNSERIALIZE_SCALAR(nlu);
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117 118 panic("Need to properly unserialize TLB\n");
| 231 232 panic("Need to properly unserialize TLB\n");
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119 for (int i = 0; i < size; i++) { 120 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 121 }
| |
122} 123 124void 125TLB::regStats() 126{ 127 read_hits 128 .name(name() + ".read_hits") 129 .desc("DTB read hits") 130 ; 131 132 read_misses 133 .name(name() + ".read_misses") 134 .desc("DTB read misses") 135 ; 136 137 138 read_accesses 139 .name(name() + ".read_accesses") 140 .desc("DTB read accesses") 141 ; 142 143 write_hits 144 .name(name() + ".write_hits") 145 .desc("DTB write hits") 146 ; 147 148 write_misses 149 .name(name() + ".write_misses") 150 .desc("DTB write misses") 151 ; 152 153 154 write_accesses 155 .name(name() + ".write_accesses") 156 .desc("DTB write accesses") 157 ; 158 159 hits 160 .name(name() + ".hits") 161 .desc("DTB hits") 162 ; 163 164 misses 165 .name(name() + ".misses") 166 .desc("DTB misses") 167 ; 168 169 invalids 170 .name(name() + ".invalids") 171 .desc("DTB access violations") 172 ; 173 174 accesses 175 .name(name() + ".accesses") 176 .desc("DTB accesses") 177 ; 178 179 hits = read_hits + write_hits; 180 misses = read_misses + write_misses; 181 accesses = read_accesses + write_accesses; 182} 183 184Fault
| 233} 234 235void 236TLB::regStats() 237{ 238 read_hits 239 .name(name() + ".read_hits") 240 .desc("DTB read hits") 241 ; 242 243 read_misses 244 .name(name() + ".read_misses") 245 .desc("DTB read misses") 246 ; 247 248 249 read_accesses 250 .name(name() + ".read_accesses") 251 .desc("DTB read accesses") 252 ; 253 254 write_hits 255 .name(name() + ".write_hits") 256 .desc("DTB write hits") 257 ; 258 259 write_misses 260 .name(name() + ".write_misses") 261 .desc("DTB write misses") 262 ; 263 264 265 write_accesses 266 .name(name() + ".write_accesses") 267 .desc("DTB write accesses") 268 ; 269 270 hits 271 .name(name() + ".hits") 272 .desc("DTB hits") 273 ; 274 275 misses 276 .name(name() + ".misses") 277 .desc("DTB misses") 278 ; 279 280 invalids 281 .name(name() + ".invalids") 282 .desc("DTB access violations") 283 ; 284 285 accesses 286 .name(name() + ".accesses") 287 .desc("DTB accesses") 288 ; 289 290 hits = read_hits + write_hits; 291 misses = read_misses + write_misses; 292 accesses = read_accesses + write_accesses; 293} 294 295Fault
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185TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
| 296TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
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186{
| 297{
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| 298 return NoFault; 299} 300 301Fault 302TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 303 uint8_t domain, bool sNp) 304{ 305 return NoFault; 306} 307 308#if !FULL_SYSTEM 309Fault 310TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 311 Translation *translation, bool &delay, bool timing) 312{ 313 // XXX Cache misc registers and have miscreg write function inv cache
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187 Addr vaddr = req->getVaddr() & ~PcModeMask; 188 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 189 uint32_t flags = req->getFlags(); 190
| 314 Addr vaddr = req->getVaddr() & ~PcModeMask; 315 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 316 uint32_t flags = req->getFlags(); 317
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191 if (mode != Execute) { 192 assert(flags & MustBeOne);
| 318 bool is_fetch = (mode == Execute); 319 bool is_write = (mode == Write);
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193
| 320
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194 if (sctlr.a || (flags & AllowUnaligned) == 0) { 195 if ((vaddr & flags & AlignmentMask) != 0) { 196 return new DataAbort(vaddr, (mode == Write), 0, 197 ArmFault::AlignmentFault);
| 321 if (!is_fetch) { 322 assert(flags & MustBeOne); 323 if (sctlr.a || !(flags & AllowUnaligned)) { 324 if (vaddr & flags & AlignmentMask) { 325 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
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198 } 199 } 200 }
| 326 } 327 } 328 }
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201#if !FULL_SYSTEM 202 Process * p = tc->getProcessPtr();
| |
203 204 Addr paddr;
| 329 330 Addr paddr;
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| 331 Process *p = tc->getProcessPtr(); 332
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205 if (!p->pTable->translate(vaddr, paddr)) 206 return Fault(new GenericPageTableFault(vaddr)); 207 req->setPaddr(paddr); 208 209 return NoFault;
| 333 if (!p->pTable->translate(vaddr, paddr)) 334 return Fault(new GenericPageTableFault(vaddr)); 335 req->setPaddr(paddr); 336 337 return NoFault;
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210#else
| 338} 339 340#else // FULL_SYSTEM 341 342Fault 343TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 344 Translation *translation, bool &delay, bool timing) 345{ 346 // XXX Cache misc registers and have miscreg write function inv cache 347 Addr vaddr = req->getVaddr() & ~PcModeMask; 348 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 350 uint32_t flags = req->getFlags(); 351 352 bool is_fetch = (mode == Execute); 353 bool is_write = (mode == Write); 354 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 355 356 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 357 & UserMode); 358 if (!is_fetch) { 359 assert(flags & MustBeOne); 360 if (sctlr.a || !(flags & AllowUnaligned)) { 361 if (vaddr & flags & AlignmentMask) { 362 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 363 } 364 } 365 } 366 367 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 368 Fault fault; 369 370
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211 if (!sctlr.m) { 212 req->setPaddr(vaddr);
| 371 if (!sctlr.m) { 372 req->setPaddr(vaddr);
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| 373 if (sctlr.tre == 0) { 374 req->setFlags(Request::UNCACHEABLE); 375 } else { 376 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 377 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 378 379 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 380 req->setFlags(Request::UNCACHEABLE); 381 } 382 return trickBoxCheck(req, mode, 0, false); 383 } 384 385 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 386 // Translation enabled 387 388 TlbEntry *te = lookup(vaddr, context_id); 389 if (te == NULL) { 390 // start translation table walk, pass variables rather than 391 // re-retreaving in table walker for speed 392 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 393 vaddr, context_id); 394 fault = tableWalker->walk(req, tc, context_id, mode, translation, 395 timing); 396 if (timing) 397 delay = true; 398 if (fault) 399 return fault; 400 401 te = lookup(vaddr, context_id); 402 if (!te) 403 printTlb(); 404 assert(te); 405 } 406 407 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 408 switch ( (dacr >> (te->domain * 2)) & 0x3) { 409 case 0: 410 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 411 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 412 if (is_fetch) 413 return new PrefetchAbort(vaddr, 414 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 415 else 416 return new DataAbort(vaddr, te->domain, is_write, 417 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 418 case 1: 419 // Continue with permissions check 420 break; 421 case 2: 422 panic("UNPRED domain\n"); 423 case 3: 424 req->setPaddr(te->pAddr(vaddr)); 425 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 426 if (fault) 427 return fault;
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213 return NoFault; 214 }
| 428 return NoFault; 429 }
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215 warn_once("MPU translation not implemented\n"); 216 req->setPaddr(vaddr);
| 430 431 uint8_t ap = te->ap; 432 433 if (sctlr.afe == 1) 434 ap |= 1; 435 436 bool abt; 437 438 switch (ap) { 439 case 0: 440 abt = true; 441 break; 442 case 1: 443 abt = !is_priv; 444 break; 445 case 2: 446 abt = !is_priv && is_write; 447 break; 448 case 3: 449 abt = false; 450 break; 451 case 4: 452 panic("UNPRED premissions\n"); 453 case 5: 454 abt = !is_priv || is_write; 455 break; 456 case 6: 457 case 7: 458 abt = is_write; 459 break; 460 default: 461 panic("Unknown permissions\n"); 462 } 463 if ((is_fetch) && (abt || te->xn)) { 464 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 465 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 466 return new PrefetchAbort(vaddr, 467 (te->sNp ? ArmFault::Permission0 : 468 ArmFault::Permission1)); 469 } else if (abt) { 470 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 471 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 472 return new DataAbort(vaddr, te->domain, is_write, 473 (te->sNp ? ArmFault::Permission0 : 474 ArmFault::Permission1)); 475 } 476 477 req->setPaddr(te->pAddr(vaddr)); 478 // Check for a trickbox generated address fault 479 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 480 if (fault) 481 return fault; 482
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217 return NoFault;
| 483 return NoFault;
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218
| 484}
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219 220#endif
| 485 486#endif
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| 487 488Fault 489TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 490{ 491 bool delay = false; 492 Fault fault; 493#if FULL_SYSTEM 494 fault = translateFs(req, tc, mode, NULL, delay, false); 495#else 496 fault = translateSe(req, tc, mode, NULL, delay, false); 497#endif 498 assert(!delay); 499 return fault;
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221} 222
| 500} 501
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223void
| 502Fault
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224TLB::translateTiming(RequestPtr req, ThreadContext *tc, 225 Translation *translation, Mode mode) 226{ 227 assert(translation);
| 503TLB::translateTiming(RequestPtr req, ThreadContext *tc, 504 Translation *translation, Mode mode) 505{ 506 assert(translation);
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228 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
| 507 bool delay = false; 508 Fault fault; 509#if FULL_SYSTEM 510 fault = translateFs(req, tc, mode, translation, delay, true); 511#else 512 fault = translateSe(req, tc, mode, translation, delay, true); 513#endif 514 if (!delay) 515 translation->finish(fault, req, tc, mode); 516 return fault;
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229} 230 231ArmISA::TLB * 232ArmTLBParams::create() 233{ 234 return new ArmISA::TLB(this); 235}
| 517} 518 519ArmISA::TLB * 520ArmTLBParams::create() 521{ 522 return new ArmISA::TLB(this); 523}
|