1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007 MIPS Technologies, Inc.
16 * Copyright (c) 2007-2008 The Florida State University
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Nathan Binkert
43 * Steve Reinhardt
44 * Jaidev Patwardhan
45 * Stephen Hines
46 */
47
48#include <string>
49#include <vector>
50
51#include "arch/arm/faults.hh"
52#include "arch/arm/pagetable.hh"
53#include "arch/arm/tlb.hh"
54#include "arch/arm/utility.hh"
55#include "base/inifile.hh"
56#include "base/str.hh"
57#include "base/trace.hh"
58#include "cpu/thread_context.hh"
59#include "mem/page_table.hh"
60#include "params/ArmTLB.hh"
61#include "sim/process.hh"
62
63
64using namespace std;
65using namespace ArmISA;
66
67///////////////////////////////////////////////////////////////////////
68//
69// ARM TLB
70//
71
72#define MODE2MASK(X) (1 << (X))
73
74TLB::TLB(const Params *p)
75 : BaseTLB(p), size(p->size), nlu(0)
76{
77 table = new ArmISA::PTE[size];
78 memset(table, 0, sizeof(ArmISA::PTE[size]));
79 smallPages=0;
80}
81
82TLB::~TLB()
83{
84 if (table)
85 delete [] table;
86}
87
88// look up an entry in the TLB
89ArmISA::PTE *
90TLB::lookup(Addr vpn, uint8_t asn) const
91{
92 // assume not found...
93 ArmISA::PTE *retval = NULL;
94 PageTable::const_iterator i = lookupTable.find(vpn);
95 if (i != lookupTable.end()) {
96 while (i->first == vpn) {
97 int index = i->second;
98 ArmISA::PTE *pte = &table[index];
99
100 /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
101 Addr Mask = pte->Mask;
102 Addr InvMask = ~Mask;
103 Addr VPN = pte->VPN;
104 // warn("Valid: %d - %d\n",pte->V0,pte->V1);
105 if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
106 { // We have a VPN + ASID Match
107 retval = pte;
108 break;
109 }
110 ++i;
111 }
112 }
113
114 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
115 retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
116 return retval;
117}
118
119ArmISA::PTE* TLB::getEntry(unsigned Index) const
120{
121 // Make sure that Index is valid
122 assert(Index<size);
123 return &table[Index];
124}
125
126int TLB::probeEntry(Addr vpn,uint8_t asn) const
127{
128 // assume not found...
129 ArmISA::PTE *retval = NULL;
130 int Ind=-1;
131 PageTable::const_iterator i = lookupTable.find(vpn);
132 if (i != lookupTable.end()) {
133 while (i->first == vpn) {
134 int index = i->second;
135 ArmISA::PTE *pte = &table[index];
136
137 /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
138 Addr Mask = pte->Mask;
139 Addr InvMask = ~Mask;
140 Addr VPN = pte->VPN;
141 if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
142 { // We have a VPN + ASID Match
143 retval = pte;
144 Ind = index;
145 break;
146 }
147
148 ++i;
149 }
150 }
151 DPRINTF(Arm,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
152 return Ind;
153}
154Fault inline
155TLB::checkCacheability(RequestPtr &req)
156{
157 Addr VAddrUncacheable = 0xA0000000;
158 // In ARM, cacheability is controlled by certain bits of the virtual address
159 // or by the TLB entry
160 if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
161 // mark request as uncacheable
162 req->setFlags(Request::UNCACHEABLE);
163 }
164 return NoFault;
165}
166void TLB::insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages)
167{
168 smallPages=_smallPages;
169 if(Index > size){
170 warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);
171 } else {
172 // Update TLB
173 DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
174 ((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
175 if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid
176 PageTable::iterator i = lookupTable.find(table[Index].VPN);
177 lookupTable.erase(i);
178 }
179 table[Index]=pte;
180 // Update fast lookup table
181 lookupTable.insert(make_pair(table[Index].VPN, Index));
182 // int TestIndex=probeEntry(pte.VPN,pte.asid);
183 // warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
184 }
185
186}
187
188// insert a new TLB entry
189void
190TLB::insert(Addr addr, ArmISA::PTE &pte)
191{
192 fatal("TLB Insert not yet implemented\n");
193}
194
195void
196TLB::flushAll()
197{
198 DPRINTF(TLB, "flushAll\n");
199 memset(table, 0, sizeof(ArmISA::PTE[size]));
200 lookupTable.clear();
201 nlu = 0;
202}
203
204void
205TLB::serialize(ostream &os)
206{
207 SERIALIZE_SCALAR(size);
208 SERIALIZE_SCALAR(nlu);
209
210 for (int i = 0; i < size; i++) {
211 nameOut(os, csprintf("%s.PTE%d", name(), i));
212 table[i].serialize(os);
213 }
214}
215
216void
217TLB::unserialize(Checkpoint *cp, const string §ion)
218{
219 UNSERIALIZE_SCALAR(size);
220 UNSERIALIZE_SCALAR(nlu);
221
222 for (int i = 0; i < size; i++) {
223 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
224 if (table[i].V0 || table[i].V1) {
225 lookupTable.insert(make_pair(table[i].VPN, i));
226 }
227 }
228}
229
230void
231TLB::regStats()
232{
233 read_hits
234 .name(name() + ".read_hits")
235 .desc("DTB read hits")
236 ;
237
238 read_misses
239 .name(name() + ".read_misses")
240 .desc("DTB read misses")
241 ;
242
243
244 read_accesses
245 .name(name() + ".read_accesses")
246 .desc("DTB read accesses")
247 ;
248
249 write_hits
250 .name(name() + ".write_hits")
251 .desc("DTB write hits")
252 ;
253
254 write_misses
255 .name(name() + ".write_misses")
256 .desc("DTB write misses")
257 ;
258
259
260 write_accesses
261 .name(name() + ".write_accesses")
262 .desc("DTB write accesses")
263 ;
264
265 hits
266 .name(name() + ".hits")
267 .desc("DTB hits")
268 ;
269
270 misses
271 .name(name() + ".misses")
272 .desc("DTB misses")
273 ;
274
275 invalids
276 .name(name() + ".invalids")
277 .desc("DTB access violations")
278 ;
279
280 accesses
281 .name(name() + ".accesses")
282 .desc("DTB accesses")
283 ;
284
285 hits = read_hits + write_hits;
286 misses = read_misses + write_misses;
287 accesses = read_accesses + write_accesses;
288}
289
290Fault
291TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
292{
293 Addr vaddr = req->getVaddr() & ~PcModeMask;
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007 MIPS Technologies, Inc.
16 * Copyright (c) 2007-2008 The Florida State University
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Nathan Binkert
43 * Steve Reinhardt
44 * Jaidev Patwardhan
45 * Stephen Hines
46 */
47
48#include <string>
49#include <vector>
50
51#include "arch/arm/faults.hh"
52#include "arch/arm/pagetable.hh"
53#include "arch/arm/tlb.hh"
54#include "arch/arm/utility.hh"
55#include "base/inifile.hh"
56#include "base/str.hh"
57#include "base/trace.hh"
58#include "cpu/thread_context.hh"
59#include "mem/page_table.hh"
60#include "params/ArmTLB.hh"
61#include "sim/process.hh"
62
63
64using namespace std;
65using namespace ArmISA;
66
67///////////////////////////////////////////////////////////////////////
68//
69// ARM TLB
70//
71
72#define MODE2MASK(X) (1 << (X))
73
74TLB::TLB(const Params *p)
75 : BaseTLB(p), size(p->size), nlu(0)
76{
77 table = new ArmISA::PTE[size];
78 memset(table, 0, sizeof(ArmISA::PTE[size]));
79 smallPages=0;
80}
81
82TLB::~TLB()
83{
84 if (table)
85 delete [] table;
86}
87
88// look up an entry in the TLB
89ArmISA::PTE *
90TLB::lookup(Addr vpn, uint8_t asn) const
91{
92 // assume not found...
93 ArmISA::PTE *retval = NULL;
94 PageTable::const_iterator i = lookupTable.find(vpn);
95 if (i != lookupTable.end()) {
96 while (i->first == vpn) {
97 int index = i->second;
98 ArmISA::PTE *pte = &table[index];
99
100 /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
101 Addr Mask = pte->Mask;
102 Addr InvMask = ~Mask;
103 Addr VPN = pte->VPN;
104 // warn("Valid: %d - %d\n",pte->V0,pte->V1);
105 if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
106 { // We have a VPN + ASID Match
107 retval = pte;
108 break;
109 }
110 ++i;
111 }
112 }
113
114 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
115 retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
116 return retval;
117}
118
119ArmISA::PTE* TLB::getEntry(unsigned Index) const
120{
121 // Make sure that Index is valid
122 assert(Index<size);
123 return &table[Index];
124}
125
126int TLB::probeEntry(Addr vpn,uint8_t asn) const
127{
128 // assume not found...
129 ArmISA::PTE *retval = NULL;
130 int Ind=-1;
131 PageTable::const_iterator i = lookupTable.find(vpn);
132 if (i != lookupTable.end()) {
133 while (i->first == vpn) {
134 int index = i->second;
135 ArmISA::PTE *pte = &table[index];
136
137 /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
138 Addr Mask = pte->Mask;
139 Addr InvMask = ~Mask;
140 Addr VPN = pte->VPN;
141 if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
142 { // We have a VPN + ASID Match
143 retval = pte;
144 Ind = index;
145 break;
146 }
147
148 ++i;
149 }
150 }
151 DPRINTF(Arm,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
152 return Ind;
153}
154Fault inline
155TLB::checkCacheability(RequestPtr &req)
156{
157 Addr VAddrUncacheable = 0xA0000000;
158 // In ARM, cacheability is controlled by certain bits of the virtual address
159 // or by the TLB entry
160 if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
161 // mark request as uncacheable
162 req->setFlags(Request::UNCACHEABLE);
163 }
164 return NoFault;
165}
166void TLB::insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages)
167{
168 smallPages=_smallPages;
169 if(Index > size){
170 warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);
171 } else {
172 // Update TLB
173 DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
174 ((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
175 if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid
176 PageTable::iterator i = lookupTable.find(table[Index].VPN);
177 lookupTable.erase(i);
178 }
179 table[Index]=pte;
180 // Update fast lookup table
181 lookupTable.insert(make_pair(table[Index].VPN, Index));
182 // int TestIndex=probeEntry(pte.VPN,pte.asid);
183 // warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
184 }
185
186}
187
188// insert a new TLB entry
189void
190TLB::insert(Addr addr, ArmISA::PTE &pte)
191{
192 fatal("TLB Insert not yet implemented\n");
193}
194
195void
196TLB::flushAll()
197{
198 DPRINTF(TLB, "flushAll\n");
199 memset(table, 0, sizeof(ArmISA::PTE[size]));
200 lookupTable.clear();
201 nlu = 0;
202}
203
204void
205TLB::serialize(ostream &os)
206{
207 SERIALIZE_SCALAR(size);
208 SERIALIZE_SCALAR(nlu);
209
210 for (int i = 0; i < size; i++) {
211 nameOut(os, csprintf("%s.PTE%d", name(), i));
212 table[i].serialize(os);
213 }
214}
215
216void
217TLB::unserialize(Checkpoint *cp, const string §ion)
218{
219 UNSERIALIZE_SCALAR(size);
220 UNSERIALIZE_SCALAR(nlu);
221
222 for (int i = 0; i < size; i++) {
223 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
224 if (table[i].V0 || table[i].V1) {
225 lookupTable.insert(make_pair(table[i].VPN, i));
226 }
227 }
228}
229
230void
231TLB::regStats()
232{
233 read_hits
234 .name(name() + ".read_hits")
235 .desc("DTB read hits")
236 ;
237
238 read_misses
239 .name(name() + ".read_misses")
240 .desc("DTB read misses")
241 ;
242
243
244 read_accesses
245 .name(name() + ".read_accesses")
246 .desc("DTB read accesses")
247 ;
248
249 write_hits
250 .name(name() + ".write_hits")
251 .desc("DTB write hits")
252 ;
253
254 write_misses
255 .name(name() + ".write_misses")
256 .desc("DTB write misses")
257 ;
258
259
260 write_accesses
261 .name(name() + ".write_accesses")
262 .desc("DTB write accesses")
263 ;
264
265 hits
266 .name(name() + ".hits")
267 .desc("DTB hits")
268 ;
269
270 misses
271 .name(name() + ".misses")
272 .desc("DTB misses")
273 ;
274
275 invalids
276 .name(name() + ".invalids")
277 .desc("DTB access violations")
278 ;
279
280 accesses
281 .name(name() + ".accesses")
282 .desc("DTB accesses")
283 ;
284
285 hits = read_hits + write_hits;
286 misses = read_misses + write_misses;
287 accesses = read_accesses + write_accesses;
288}
289
290Fault
291TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
292{
293 Addr vaddr = req->getVaddr() & ~PcModeMask;
|